diff options
| author | Yue Du <daviddu@us.ibm.com> | 2016-02-29 22:39:41 -0600 |
|---|---|---|
| committer | Prachi Gupta <pragupta@us.ibm.com> | 2016-06-08 11:45:54 -0500 |
| commit | 534db91fb2b79d46478459447e36dfde68dc5c7a (patch) | |
| tree | 8f2c8f5d59adde4a4e13ecaaa66bd6cb48db91b6 /import/chips/p9/procedures/hwp/cache | |
| parent | fef534cb390af83ba62bda8e0162bab0108a5e30 (diff) | |
| download | talos-sbe-534db91fb2b79d46478459447e36dfde68dc5c7a.tar.gz talos-sbe-534db91fb2b79d46478459447e36dfde68dc5c7a.zip | |
HWP-CACHE/CORE:istep4 procedures updates
Change-Id: I8c1e08f5db655db54a91bb0ab4dab91b83f2eaef
Original-Change-Id: I707a936f8124f997c338ce01db205b958716a8da
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/21489
Tested-by: Jenkins Server
Tested-by: Hostboot CI
Tested-by: PPE CI
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25113
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'import/chips/p9/procedures/hwp/cache')
| -rw-r--r-- | import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.C | 72 | ||||
| -rw-r--r-- | import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.H | 59 |
2 files changed, 131 insertions, 0 deletions
diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.C b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.C new file mode 100644 index 00000000..932fd0f4 --- /dev/null +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.C @@ -0,0 +1,72 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_dpll_initf.C +/// @brief Load DPLL ring for EX non-core +/// +/// Procedure Summary: +/// Load cache ring images from MVPD +/// These rings must contain ALL chip customization data. +/// This includes the following: DPLL Power headers, and DTS +/// Historically this was stored in MVPD keywords are #R, #G. Still stored in +/// MVPD, but SBE image is customized with rings for booting cores + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 2 + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include "p9_hcd_cache_dpll_initf.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: Load DPLL ring for cache +//------------------------------------------------------------------------------ + +fapi2::ReturnCode +p9_hcd_cache_dpll_initf( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target) +{ + FAPI_INF(">>p9_hcd_cache_dpll_initf"); + +#ifndef P9_HCD_STOP_SKIP_SCAN + + FAPI_DBG("Scanning Cache DPLL FUNC Rings"); + FAPI_TRY(fapi2::putRing(i_target, EQ_DPLL_FUNC, + fapi2::RING_MODE_HEADER_CHECK)); + +fapi_try_exit: + +#endif + + FAPI_INF("<<p9_hcd_cache_dpll_initf"); + return fapi2::current_err; +} + + + diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.H b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.H new file mode 100644 index 00000000..0b059c96 --- /dev/null +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.H @@ -0,0 +1,59 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_dpll_initf.H +/// @brief Load DPLL ring for EX non-core +/// + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 2 + +#ifndef __P9_HCD_CACHE_DPLL_INITF_H__ +#define __P9_HCD_CACHE_DPLL_INITF_H__ + +#include <fapi2.H> + +/// @typedef p9_hcd_cache_dpll_initf_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_dpll_initf_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>&); + +extern "C" +{ + +/// @brief Load DPLL ring for EX non-core +/// +/// @param [in] i_target TARGET_TYPE_EQ target +/// +/// @attr +/// @attritem ATTR_CACHE_DPLL_RING - EX target, uint32 +/// pointer to RS4 content, VPD #R Keyword content(RS4)<br> +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_cache_dpll_initf( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target); + +} + +#endif // __P9_HCD_CACHE_DPLL_INITF_H__ |
