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* ARM: socfpga: move SoC sources to mach-socfpgaMasahiro Yamada2015-05-071-229/+0
| | | | | | Our recent trend is to collect SoC files into arch/arm/mach-(SOC). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* arm: socfpga: spl: add board_init_f to SPLDinh Nguyen2015-04-211-0/+29
| | | | | | | Remap SDRAM to 0x0, and clear OCRAM's ECC in board_init_f(). Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Reviewed-by: Marek Vasut <marex@denx.de>
* arm: socfpga: spl: Add SDRAM checkDinh Nguyen2015-04-211-0/+6
| | | | Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: spl: printout sdram sizeDinh Nguyen2015-04-211-0/+4
| | | | | Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Reviewed-by: Marek Vasut <marex@denx.de>
* arm: socfpga: spl: add sdram init and calibrationDinh Nguyen2015-04-211-0/+13
| | | | | | Add a call to checkboard along with sdram intilialization and calibration. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: spl: allow bootrom to enable IOs after warm resetDinh Nguyen2015-04-211-0/+3
| | | | | Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Marek Vasut <marex@denx.de>
* arm: socfpga: spl: Add call to timer_initDinh Nguyen2015-04-211-0/+2
| | | | Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: spl: enable sdram, timer and uartDinh Nguyen2015-04-211-0/+4
| | | | | | | Add the calls in the spl_board_init to enable SDRAM, timer, and UART. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Marek Vasut <marex@denx.de>
* remove unnecessary version.h includesRob Herring2015-03-241-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Various files are needlessly rebuilt every time due to the version and build time changing. As version.h is not actually needed, remove the include. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Macpaul Lin <macpaul@andestech.com> Cc: Wolfgang Denk <wd@denx.de> Cc: York Sun <yorksun@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Philippe Reynes <tremyfr@yahoo.fr> Cc: Eric Jarrige <eric.jarrige@armadeus.org> Cc: "David Müller" <d.mueller@elsoft.ch> Cc: Phil Edworthy <phil.edworthy@renesas.com> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Torsten Koschorrek <koschorrek@synertronixx.de> Cc: Anatolij Gustschin <agust@denx.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Łukasz Majewski <l.majewski@samsung.com>
* arm: socfpga: clock: Clean up bit definitionsMarek Vasut2014-10-061-74/+100
| | | | | | | | | | | | | | Clean up the clock code definitions so they are aligned with mainline standards. There are no functional changes in this patch. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* socfpga: Fix SOCFPGA build error for Altera dev kitChin Liang See2014-08-291-0/+2
| | | | | | | | | | | | | To fix the build error when build for Altera dev kit, not virtual target. At same time, set the build for Altera dev kit as default instead virtual target. With that, U-Boot is booting well and SPL still lack of few drivers. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
* socfpga: Adding Scan Manager driverChin Liang See2014-07-051-0/+4
| | | | | | | | | | | | Scan Manager driver will be called to configure the IOCSR scan chain. This configuration will setup the IO buffer settings Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
* socfpga: Adding Clock Manager driverChin Liang See2014-04-071-0/+89
| | | | | | | | | | | | | | Clock Manager driver will be called to reconfigure all the clocks setting based on user input. The input are passed to Preloader through handoff files Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Acked-by: Pavel Machek <pavel@denx.de>
* socfpga: Adding Freeze Controller driverChin Liang See2013-12-031-0/+9
| | | | | | | | | | | | | | Adding Freeze Controller driver. All HPS IOs need to be in freeze state during pin mux or IO buffer configuration. It is to avoid any glitch which might happen during the configuration from propagating to external devices. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
* socfpga: Adding System Manager driverChin Liang See2013-10-071-0/+6
| | | | | | | | | | | | | | | Adding System Manager driver which will configure the pin mux for real hardware Cyclone V development kit (not Virtual Platform) Signed-off-by: Chin Liang See <clsee@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Acked-by: Dinh Nguyen <dinguyen@altera.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-241-12/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* socfpga/spl: Remove malloc.hVikram Narayanan2012-11-041-1/+0
| | | | | | Remove unused header Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
* socfpga/spl: Remove timer_init from spl_board_initVikram Narayanan2012-11-041-3/+0
| | | | | | | | Timer is initialized already in board_init_r function in (common/spl/spl.c) No need to initialize it again Signed-off-by: Vikram Narayanan <vikram186@gmail.com> Cc: Dinh Nguyen <dinguyen@altera.com>
* ARM: Add Altera SOCFPGA Cyclone5Dinh Nguyen2012-10-041-0/+48
Add minimal support for Altera's SOCFPGA Cyclone 5 hardware. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Chin Liang See <clsee@altera.com> Signed-off-by: Pavel Machek <pavel@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Tom Trini <trini@ti.com> Cc: Wolfgang Denx <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefan Roese <sr@denx.de> ---- v8: Remove no_return attribute for reset_cpu Based on v2012.10-rc2
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