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* common: Pass the boot device into spl_boot_mode()Marek Vasut2016-06-262-2/+2
| | | | | | | | | | | | | | | | | | The SPL code already knows which boot device it calls the spl_boot_mode() on, so pass that information into the function. This allows the code of spl_boot_mode() avoid invoking spl_boot_device() again, but it also lets board_boot_order() correctly alter the behavior of the boot process. The later one is important, since in certain cases, it is desired that spl_boot_device() return value be overriden using board_boot_order(). Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> [add newly introduced zynq variant] Signed-aff-by: Andreas Bießmann <andreas@biessmann.org>
* arm: bcm235xx: update clock frameworkSteve Rae2016-06-241-5/+5
| | | | | | | | The handling of the "usage counter" is incorrect, and the clock should only be disabled when transitioning from 1 to 0. Reported-by: Chris Brand <chris.brand@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
* arm: bcm235xx: fix kps ccuChris Brand2016-06-241-5/+1
| | | | | | | The Kona Peripheral Slave CCU has 4 policy mask registers, not 8. Signed-off-by: Chris Brand <chris.brand@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
* ARM: armv7: refactor Makefile slightlyMasahiro Yamada2016-06-241-9/+2
| | | | | | Use Kbuild standard style where possible. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* omap3: bugfix in timer on rolloverDaniel Gorsulowski2016-06-241-1/+1
| | | | Signed-off-by: Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
* sunxi: Add PSCI implementation in CChen-Yu Tsai2016-06-205-504/+341
| | | | | | | | | | | | | | To make the PSCI backend more maintainable and easier to port to newer SoCs, rewrite the current PSCI implementation in C. Some inline assembly bits are required to access coprocessor registers. PSCI stack setup is the only part left completely in assembly. In theory this part could be split out of psci_arch_init into a separate common function, and psci_arch_init could be completely in C. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add base address for GICChen-Yu Tsai2016-06-202-4/+4
| | | | | | | | | Instead of hardcoding the GIC addresses in the PSCI implementation, provide a base address in the cpu header. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Make CPUCFG_BASE macro names the same across familiesChen-Yu Tsai2016-06-202-12/+12
| | | | | | | | | Use SUNXI_CPUCFG_BASE across all families. This makes writing common PSCI code easier. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* ARM: PSCI: save and restore clobbered registers in v7_flush_dcache_allChen-Yu Tsai2016-06-201-0/+2
| | | | | | Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* ARM: PSCI: use only r0 and r3 in psci_get_cpu_stack_top()Chen-Yu Tsai2016-06-201-9/+9
| | | | | | | | | | | For psci_get_cpu_stack_top() to be usable in C code, it must adhere to the ARM calling conventions. Since it could be called when the stack is still unavailable, and the entry code to linux also expects r1 and r2 to remain unchanged, stick to r0 and r3. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* board: am57xx: Rename TARGET_BEAGLE_X15 as TARGET_AM57XX_EVMLokesh Vutla2016-06-131-2/+2
| | | | | | | | | board/am57xx supports all boards based on am57xx. Rename the taget as TARGET_AM57XX_EVM. Fixes: 74cc8b097d9af ("board: ti: beagle_x15: Rename to indicate support for TI am57xx evms") Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* board: arm:: Add support for Broadcom BCM23550Steve Rae2016-06-1311-0/+1912
| | | | | | Add support for the Broadcom BCM23550 board. Signed-off-by: Steve Rae <srae@broadcom.com>
* Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-06-131-1/+4
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| * arm: Allow skipping of low-level init with I-cache onSimon Glass2016-06-121-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present CONFIG_SKIP_LOWLEVEL_INIT prevents U-Boot from calling lowlevel_init(). This means that the instruction cache is not enabled and the board runs very slowly. What is really needed in many cases is to skip the call to lowlevel_init() but still perform CP15 init. Add an option to handle this. Reviewed-by: Heiko Schocher <hs@denx.de> Tested-on: smartweb, corvus, taurus, axm Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
* | arm: dra7xx: Assign omap_vcores based on board typeKeerthy2016-06-121-78/+0
| | | | | | | | | | | | | | | | | | | | Currently omap_vcores which holds pmic data is being assigned based on the SoC type. PMIC is not a part of SoC. It is logical to to assign omap_vcores based on board type. Hence over ride the vcores_init function and assign omap_vcores based on the board type. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-06-124-35/+51
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| * imx: mx7: implement reset_miscPeng Fan2016-05-311-0/+8
| | | | | | | | | | | | | | We need to power down lcdif to make 'reset' can pass stress test. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: mx6: correct get_cpu_speed_grade_hz for i.MX6DQPPeng Fan2016-05-241-2/+2
| | | | | | | | | | | | | | | | Correct get_cpu_speed_grade_hz for i.MX6DQP, otherwise we will get wrong speed grade info i.MX6DQP. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: mx6: ddr: support i.MX6D/QPlusPeng Fan2016-05-241-2/+2
| | | | | | | | | | | | | | Support i.MX6D/QPlus. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: mx6: use simpler runtime cpu dection macrosPeng Fan2016-05-243-36/+29
| | | | | | | | | | | | | | | | Use simpler runtime cpu dection macros. i.MX6DL and i.MX6SOLO work the same, so use is_mx6sdl. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: mx6: support i.MX6SOLO when enable/disable_ldb_di_clock_sourcesPeng Fan2016-05-241-2/+2
| | | | | | | | | | | | | | | | i.MX6DL and i.MX6SOLO work the same, add i.MX6SOLO support when enable/disable_ldb_di_clock_sources. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: correct speed grading info for i.MX6ULPeng Fan2016-05-181-0/+15
| | | | | | | | | | | | | | Correct speed grading info for i.MX6UL Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* | mtd: nand: omap: allow to switch to BCH16Heiko Schocher2016-06-091-2/+4
| | | | | | | | | | | | | | support in omap_nand_switch_ecc() also an eccstrength from 16. Signed-off-by: Heiko Schocher <hs@denx.de>
* | armv7: omap-common: make SPL board_mmc_init() weakHeiko Schocher2016-06-091-1/+1
| | | | | | | | | | | | | | make this function weak, so board code can setup in SPL MMC init with board special values. Signed-off-by: Heiko Schocher <hs@denx.de>
* | arm, am335x: Enable Spread Spectrum for the MPUHeiko Schocher2016-06-091-0/+73
| | | | | | | | | | | | | | | | Enable Spread Spectrum for the MPU by calculating the required values and setting the registers accordingly. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* | Merge http://git.denx.de/u-boot-samsungTom Rini2016-06-061-0/+3
|\ \ | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: configs/peach-pi_defconfig configs/peach-pit_defconfig
| * | exynos: pwm: Add a driver for the exynos5 PWMSimon Glass2016-05-251-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | This driver supports the standard PWM API. There are 5 PWMs. Four are used normally and the last is normally used as a timer. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | armv7: fix order of OMAP die ID printingLadislav Michl2016-06-061-2/+2
| | | | | | | | | | | | | | | Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Acked-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
* | | arm: omap: Introduce vcores_init functionKeerthy2016-06-021-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | The pmic registers for variants of am57xx boards are different hence we need to assign them carefully based on the board type. Add a function to assign omap_vcores after the board detection. Signed-off-by: Keerthy <j-keerthy@ti.com>
* | | ARM: DRA7: Consolidate voltage macros across different SoCsAnna, Suman2016-06-021-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The voltage values for each voltage domain at an OPP is identical across all the SoCs in the DRA7 family. The current code defines one set of macros for DRA75x/DRA74x SoCs and another set for DRA72x macros. Consolidate both these sets into a single set. This is done so as to minimize the number of macros used when voltage values will be added for other OPPs as well. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | ARM: DRA7: Define common macros for efuse register offsetsAnna, Suman2016-06-021-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define a set of common macros for the efuse register offsets (different for each OPP) that are used to get the AVS Class 0 voltage values and ABB configuration values. Assign these common macros to the register offsets for OPP_NOM by default for all voltage domains. These common macros can then be redefined properly to point to the OPP specific efuse register offset based on the desired OPP to program a specific voltage domain. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | dra7xx: Enable USB_PHY3 32KHz clockRoger Quadros2016-06-022-2/+13
| | | | | | | | | | | | | | | | | | | | | DRA7xx has a 32KHz PHY clock for USB_PHY3 that must be enabled for USB1 instance in Super-Speed. Signed-off-by: Roger Quadros <rogerq@ti.com>
* | | ARM: OMAP5+: Provide enable/disable_usb_clocks() for CONFIG_USB_XHCI_OMAPRoger Quadros2016-06-022-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_USB_XHCI_OMAP is enabled for host mode independent of CONFIG_USB_DWC3 which is meant for gadget mode only. We need enable/disbale_usb_clocks() for host mode as well so provide for it. Fixes: 09cc14f4bcbf ("ARM: AM43xx: Add functions to enable and disable USB clocks" Signed-off-by: Roger Quadros <rogerq@ti.com>
* | | ARM: OMAP4+: Fix DPLL programming sequenceLokesh Vutla2016-05-271-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All the output clock parameters of a DPLL needs to be programmed before locking the DPLL. But it is being configured after locking the DPLL which could potentially bypass DPLL. So fixing this sequence. Reported-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com>
* | | ARM: AM33xx: Add support for Clock SynthesizerLokesh Vutla2016-05-272-0/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CDCE913 and CDCEL913 devices are modular PLL-based, low cost, high performance , programmable clock synthesizers. They generate upto 3 output clocks from a single input frequency. Each output can be programmed for any clock-frequency. Adding support for the same. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | ARM: omap5: add hooks for cpu/SoC fdt fixupsDaniel Allred2016-05-272-0/+185
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds an fdt.c file in that defines the ft_cpu_setup() function, which should be called from a board-specific ft_board_setup()). This ft_cpu_setup() will currently do nothing for non-secure (GP) devices but contains pertinent updates for booting on secure (HS) devices. Update the omap5 Makefile to include the fdt.c in the build. Signed-off-by: Daniel Allred <d-allred@ti.com> Signed-off-by: Madan Srinivas <madans@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: omap-common: Add device type to CPU stringDaniel Allred2016-05-271-2/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the CPU string output so that the device type is now included as part of the CPU string that is printed as the SPL or u-boot comes up. This update adds a suffix of the form "-GP" or "-HS" for production devices, so that general purpose (GP) and high security (HS) can be distiguished. Applies to all OMAP5 variants. Signed-off-by: Daniel Allred <d-allred@ti.com> Signed-off-by: Madan Srinivas <madans@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | spl: build: ti: add support for secure boot imagesDaniel Allred2016-05-271-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updates the SPL build so that when CONFIG_TI_SECURE_DEVICE is in use (which it should be when building for secure parts), the TI secure development package is used to create a valid secure boot image. The u-boot SPL build processes is NOT aware of the details of creating the boot image - all of that information is encapsulated in the TI secure development package, which is available from TI. More info can be found in README.ti-secure Right now, two image types are generated, MLO and X-LOADER. The types are important, as certain boot modes implemented by the device's ROM boot loader require one or the other (they are not equivalent). The output filenames are u-boot-spl_HS_MLO and u-boot-spl_HS_X-LOADER. The u-boot-spl_HS_MLO image is also copied to a file named MLO, which is the name that the device ROM bootloader requires for loading from the FAT partition of an SD card (same as on non-secure devices). Signed-off-by: Daniel Allred <d-allred@ti.com> Signed-off-by: Madan Srinivas <madans@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ti: AM43xx: config.mk: Add support for generating secure boot imagesDaniel Allred2016-05-271-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modifies the config.mk to build secure images when building the SPL for secure devices. Depending on the boot media, different images are needed for secure devices. The build generates u-boot*_HS_* files as appropriate for the different boot modes. The same u-boot binary file is processed slightly differently to produce a different boot image, depending on whether the user wants to boot off SPI, QSPI or other boot media. Refer to README.ti-secure for more information. Signed-off-by: Madan Srinivas <madans@ti.com> Signed-off-by: Daniel Allred <d-allred@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ti: omap-common: Add commands for generating secure SPL imagesDaniel Allred2016-05-271-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds a centralized config_secure.mk in omap-common for OMAP-style TI secure devices to use for boot image generation Depending on the boot media, different images are needed for secure devices. These commands generates u-boot*_HS_* files that need to be used to boot secure devices. Please refer to README.ti-secure for more information. Signed-off-by: Daniel Allred <d-allred@ti.com> Signed-off-by: Madan Srinivas <madans@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ti: omap-common: Add Kconfig file for secure device supportMadan Srinivas2016-05-271-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Defines CONFIG_TI_SECURE_DEVICE which needs to be turned on when building images for secure devices. This flag is used to invoke the secure image creation tools for creating a boot image that can be used on secure devices. This flag may also be used to conditionally compile code specific to secure devices. This terminology will be used by all OMAP architecture devices, hence introducing to a common location. With the creation of Kconfig for omap-common, moved the sourcing of the Kconfig files for the omap3/4/5 and am33xx devices from arch/arm/KConfig to the omap-common one. Signed-off-by: Madan Srinivas <madans@ti.com> Signed-off-by: Daniel Allred <d-allred@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | arm: Kconfig: Add support for AM43xx SoC specific KconfigMadan Srinivas2016-05-271-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding support for AM43xx secure devices require the addition of some SOC specific config options like the amount of memory used by public ROM and the address of the entry point of u-boot or SPL, as seen by the ROM code, for the image to be built correctly. This mandates the addition of am AM43xx CONFIG option and the ARM Kconfig file has been modified to source this SOC Kconfig file. Moving the TARGET_AM43XX_EVM config option to the SOC KConfig and out of the arch/arm/Kconfig. Updating defconfigs to add the CONFIG_AM43XX=y statement and removing the #define CONFIG_AM43XX from the header file. Signed-off-by: Madan Srinivas <madans@ti.com> Signed-off-by: Daniel Allred <d-allred@ti.com> Tested-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | arm: am33xx: Kconfig: Add secure device definitionsMadan Srinivas2016-05-271-0/+27
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds a new Kconfig file for AM33xx class devices. We need a common place to define CONFIG parameters for these SOCs, especially for adding support for secure devices. a) Adds a definition for ISW_ENTRY_ADDR. This is the address to which the ROM branches when the SOC ROM hands off execution to the boot loader. CONFIG_SYS_TEXT_BASE and CONFIG_SPL_TEXT_BASE are set to this value for AM43xx devices. b) Adds CONFIG_PUB_ROM_DATA_SIZE which is used to calculate CONFIG_SPL_MAX_SIZE. This value indicates the amount of memory needed by the ROM to store data during the boot process. Currently, these CONFIG options are used only by AM43xx, but in future other AM33xx class SOCs will also use them. Signed-off-by: Madan Srinivas <madans@ti.com> Signed-off-by: Daniel Allred <d-allred@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-05-241-1/+1
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| * armv7: ls102xa: spl: fix the macro name of MMC modeQianyu Gong2016-05-181-1/+1
| | | | | | | | | | | | | | MMCSD_MODE_FAT has been renamed to MMCSD_MODE_FS by commit 205b4f33. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | imx: imx7d: fix ahb clock mux 1Stefan Agner2016-05-171-1/+1
|/ | | | | | | | | | | | | | The clock parent of the AHB root clock when using mux option 1 is the SYS PLL 270MHz clock. This is specified in Table 5-11 Clock Root Table of the i.MX 7Dual Applications Processor Reference Manual. While it could be a documentation error, the 270MHz parent is also mentioned in the boot ROM configuration in Table 6-28: The clock is by default at 135MHz due to a POST_PODF value of 1 (=> divider of 2). Signed-off-by: Stefan Agner <stefan@agner.ch>
* ARM: am33xx: Fix DDR initialization delaysRuss Dill2016-05-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | The current delays in the DDR initialization routines for am33xx architectures are sometimes not running long enough leading to DDR init errors. On am437x, this shows up as an L3 NOC error after the kernel boots. This is due to the timer not being initialized properly, but instead still containing the timer init values from the boot ROM which cause timers to expire in 1/4th the time required. timer_init is typically not called until board_init_r, however on am33xx/am43xx udelay is required in sdram_init which is called from board_init_f, so a call to timer_init is required earlier. Note that this issue introduced in v2015.01 by: b352dde "am33xx: Drop timer_init call from s_init". Although this could instead fixed by reverting said commit, it would cause timer_init to be called twice in both SPL and non-SPL cases. This gives a little more fine grained control and also matches what is being done on omap-command and fsl-layerscape. Signed-off-by: Russ Dill <russ.dill@ti.com>
* Revert "omap3: Use raw SPL by default for mmc1"Tom Rini2016-05-021-0/+2
| | | | | | | | | | | | | Unfortunately with this change we now are unable to do FS mode boots from MMC1 as with the way the code works today we will always load and assume that the hard-coded raw location contains U-Boot. Further, we cannot fix this by just changing other logic to try FS-then-RAW as it would also make us have to ignore what order the ROM is telling us to try. This reverts commit 22d90d560a2b01c47f180e196e6c6485eb8e65db. Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: Add ABB setup for all domainsNishanth Menon2016-04-253-0/+40
| | | | | | | | | | | | | ABB should be initialized for all required domains voltage domain for DRA7: IVA, GPU, EVE in addition to the existing MPU domain. If we do not do this, kernel configuring just the frequency using the default boot loader configured voltage can fail on many corner lot units and has been hard to debug. This specifically is a concern with DRA7 generation of SoCs since other than VDD_MPU, all other domains are only permitted to setup the voltages to required OPP only at boot. Reported-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: OMAP5: Enable ABB configuration for MM voltage domainNishanth Menon2016-04-253-0/+14
| | | | | | | | | | Since we setup the voltage and frequency for the MM domain, we *must* setup the ABB configuration needed for the domain as well. If we do not do this, kernel configuring just the frequency using the default boot loader configured voltage can fail on many corner lot units. Reported-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
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