summaryrefslogtreecommitdiffstats
path: root/arch/arm/cpu
Commit message (Collapse)AuthorAgeFilesLines
* arm/arm1176: Aspeed start.S hackJoel Stanley2016-07-271-4/+4
| | | | | | This was included by Apseed in their SDK. Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: AST2500: add supportJoel Stanley2016-07-272-0/+24
| | | | | | Extracted from ast_sdk.v00.03.21 which is based on u-boot v2013. Signed-off-by: Joel Stanley <joel@jms.id.au>
* armv8: Enable CPUECTLR.SMPEN for coherencyMingkai Hu2016-07-081-0/+8
| | | | | | | | | | | | | | | | For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is set. The SMPEN bit should be set before enabling the data cache. If not enabled, the cache is not coherent with other cores and data corruption could occur. For A57/A72, SMPEN bit enables the processor to receive instruction cache and TLB maintenance operations broadcast from other processors in the cluster. This bit should be set before enabling the caches and MMU, or performing any cache and TLB maintenance operations. Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-06-282-5/+7
|\
| * armv8: fsl-layerscape: Append "A" in SoC name for ARM based SoCsPrabhakar Kushwaha2016-06-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | Freescale ARMv8 SoC name ends with "A" to represent ARM SoCs. like LS2080A, LS1043A, LS1012A. So append "A" to SoC names. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8/fsl_lsch2: Correct the cores frequency initializationHou Zhiqiang2016-06-241-3/+5
| | | | | | | | | | | | | | | | The register CLKCNCSR controls the frequency of all cores in the same cluster. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | common: Pass the boot device into spl_boot_mode()Marek Vasut2016-06-265-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPL code already knows which boot device it calls the spl_boot_mode() on, so pass that information into the function. This allows the code of spl_boot_mode() avoid invoking spl_boot_device() again, but it also lets board_boot_order() correctly alter the behavior of the boot process. The later one is important, since in certain cases, it is desired that spl_boot_device() return value be overriden using board_boot_order(). Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> [add newly introduced zynq variant] Signed-aff-by: Andreas Bießmann <andreas@biessmann.org>
* | arm: bcm235xx: update clock frameworkSteve Rae2016-06-241-5/+5
| | | | | | | | | | | | | | | | The handling of the "usage counter" is incorrect, and the clock should only be disabled when transitioning from 1 to 0. Reported-by: Chris Brand <chris.brand@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
* | arm: bcm235xx: fix kps ccuChris Brand2016-06-241-5/+1
| | | | | | | | | | | | | | The Kona Peripheral Slave CCU has 4 policy mask registers, not 8. Signed-off-by: Chris Brand <chris.brand@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
* | ARM: armv7: refactor Makefile slightlyMasahiro Yamada2016-06-241-9/+2
| | | | | | | | | | | | Use Kbuild standard style where possible. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | arm64: optimize smp_kick_all_cpusMasahiro Yamada2016-06-241-3/+1
| | | | | | | | | | | | | | | | gic_kick_secondary_cpus can directly return to the caller of smp_kick_all_cpus. We do not have to use x29 register here. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | omap3: bugfix in timer on rolloverDaniel Gorsulowski2016-06-241-1/+1
|/ | | | Signed-off-by: Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
* sunxi: Add PSCI implementation in CChen-Yu Tsai2016-06-205-504/+341
| | | | | | | | | | | | | | To make the PSCI backend more maintainable and easier to port to newer SoCs, rewrite the current PSCI implementation in C. Some inline assembly bits are required to access coprocessor registers. PSCI stack setup is the only part left completely in assembly. In theory this part could be split out of psci_arch_init into a separate common function, and psci_arch_init could be completely in C. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add base address for GICChen-Yu Tsai2016-06-202-4/+4
| | | | | | | | | Instead of hardcoding the GIC addresses in the PSCI implementation, provide a base address in the cpu header. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Make CPUCFG_BASE macro names the same across familiesChen-Yu Tsai2016-06-202-12/+12
| | | | | | | | | Use SUNXI_CPUCFG_BASE across all families. This makes writing common PSCI code easier. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* ARM: allocate extra space for PSCI stack in secure section during link phaseChen-Yu Tsai2016-06-201-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | The PSCI implementation expects at most 2 pages worth of space reserved at the end of the secure section for its stacks. If PSCI is relocated to secure SRAM, then everything is fine. If no secure SRAM is available, and PSCI remains in main memory, the reserved memory space doesn't cover the space used by the stack. If one accesses PSCI after Linux has fully booted, the memory that should have been reserved for the PSCI stacks may have been used by the kernel or userspace, and would be corrupted. Observed after effects include the system hanging or telinit core dumping when trying to reboot. It seems the init process gets hit the most on my test bed. This fix allocates the space used by the PSCI stacks in the secure section by skipping pages in the linker script, but only when there is no secure SRAM, to avoid bloating the binary. This fix is only a stop gap. It would be better to rework the stack allocation mechanism, maybe with proper usage of CONFIG_ macros and an explicit symbol. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* ARM: PSCI: save and restore clobbered registers in v7_flush_dcache_allChen-Yu Tsai2016-06-201-0/+2
| | | | | | Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* ARM: PSCI: use only r0 and r3 in psci_get_cpu_stack_top()Chen-Yu Tsai2016-06-201-9/+9
| | | | | | | | | | | For psci_get_cpu_stack_top() to be usable in C code, it must adhere to the ARM calling conventions. Since it could be called when the stack is still unavailable, and the entry code to linux also expects r1 and r2 to remain unchanged, stick to r0 and r3. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-06-182-10/+7
|\ | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
| * armv8/ls2080: Remove workaround for erratum A008751Sriram Dash2016-06-131-10/+0
| | | | | | | | | | | | | | | | | | | | This errata a008751 is applied on Soc specific file currently.This will be moved to a file where all the errata implementation will take place for usb for fsl. This patch removes the errata workaround from soc specific file for LS2080. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
| * arm64: fsl-layerscape: add get_svr and IS_SVR_REV helperSriram Dash2016-06-131-0/+7
| | | | | | | | | | | | | | | | Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
* | board: am57xx: Rename TARGET_BEAGLE_X15 as TARGET_AM57XX_EVMLokesh Vutla2016-06-131-2/+2
| | | | | | | | | | | | | | | | | | board/am57xx supports all boards based on am57xx. Rename the taget as TARGET_AM57XX_EVM. Fixes: 74cc8b097d9af ("board: ti: beagle_x15: Rename to indicate support for TI am57xx evms") Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | armv8: s32v234: Introduce basic support for s32v234evbEddy Petrișor2016-06-135-0/+464
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial support for NXP's S32V234 SoC and S32V234EVB board. The S32V230 family is designed to support computation-intensive applications for image processing. The S32V234, as part of the S32V230 family, is a high-performance automotive processor designed to support safe computation-intensive applications in the area of vision and sensor fusion. Code originally writen by: Original-signed-off-by: Stoica Cosmin-Stefan <cosminstefan.stoica@freescale.com> Original-signed-off-by: Mihaela Martinas <Mihaela.Martinas@freescale.com> Original-signed-off-by: Eddy Petrișor <eddy.petrisor@gmail.com> Signed-off-by: Eddy Petrișor <eddy.petrisor@nxp.com>
* | board: arm:: Add support for Broadcom BCM23550Steve Rae2016-06-1311-0/+1912
| | | | | | | | | | | | Add support for the Broadcom BCM23550 board. Signed-off-by: Steve Rae <srae@broadcom.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-06-136-2/+14
|\ \
| * | arm: Allow skipping of low-level init with I-cache onSimon Glass2016-06-126-2/+14
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present CONFIG_SKIP_LOWLEVEL_INIT prevents U-Boot from calling lowlevel_init(). This means that the instruction cache is not enabled and the board runs very slowly. What is really needed in many cases is to skip the call to lowlevel_init() but still perform CP15 init. Add an option to handle this. Reviewed-by: Heiko Schocher <hs@denx.de> Tested-on: smartweb, corvus, taurus, axm Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
* | arm: dra7xx: Assign omap_vcores based on board typeKeerthy2016-06-121-78/+0
| | | | | | | | | | | | | | | | | | | | Currently omap_vcores which holds pmic data is being assigned based on the SoC type. PMIC is not a part of SoC. It is logical to to assign omap_vcores based on board type. Hence over ride the vcores_init function and assign omap_vcores based on the board type. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-06-125-37/+53
|\ \
| * | arm: mxs: Remove misleading commentsMichael Heimpold2016-06-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Both comments look like being copy & paste errors. Signed-off-by: Michael Heimpold <michael.heimpold@i2se.com> Cc: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
| * | imx: mx7: implement reset_miscPeng Fan2016-05-311-0/+8
| | | | | | | | | | | | | | | | | | | | | We need to power down lcdif to make 'reset' can pass stress test. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6: correct get_cpu_speed_grade_hz for i.MX6DQPPeng Fan2016-05-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Correct get_cpu_speed_grade_hz for i.MX6DQP, otherwise we will get wrong speed grade info i.MX6DQP. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6: ddr: support i.MX6D/QPlusPeng Fan2016-05-241-2/+2
| | | | | | | | | | | | | | | | | | | | | Support i.MX6D/QPlus. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6: use simpler runtime cpu dection macrosPeng Fan2016-05-243-36/+29
| | | | | | | | | | | | | | | | | | | | | | | | Use simpler runtime cpu dection macros. i.MX6DL and i.MX6SOLO work the same, so use is_mx6sdl. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6: support i.MX6SOLO when enable/disable_ldb_di_clock_sourcesPeng Fan2016-05-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | i.MX6DL and i.MX6SOLO work the same, add i.MX6SOLO support when enable/disable_ldb_di_clock_sources. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
| * | Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2016-05-241-1/+1
| |\ \
| * | | imx: correct speed grading info for i.MX6ULPeng Fan2016-05-181-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct speed grading info for i.MX6UL Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* | | | board: ls2080a: Add "mcinitcmd" env for MC & DPL deploymentPratiyush Mohan Srivastava2016-06-101-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Environment variable mcinitcmd is defined to initiate MC and DPL deployment from the location where it is stored (NOR, NAND, SD, SATA, USB) during booting. If this variable is not defined then macro MC_BOOT_ENV_VAR will be null and MC will not be booted and DPL will not be applied during U-boot booting. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | | armv8/ls2080a: configure PMU's PCTBENR to enable WDTYunhui Cui2016-06-101-0/+12
| |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | mtd: nand: omap: allow to switch to BCH16Heiko Schocher2016-06-091-2/+4
| | | | | | | | | | | | | | | | | | | | | support in omap_nand_switch_ecc() also an eccstrength from 16. Signed-off-by: Heiko Schocher <hs@denx.de>
* | | armv7: omap-common: make SPL board_mmc_init() weakHeiko Schocher2016-06-091-1/+1
| | | | | | | | | | | | | | | | | | | | | make this function weak, so board code can setup in SPL MMC init with board special values. Signed-off-by: Heiko Schocher <hs@denx.de>
* | | arm, am335x: Enable Spread Spectrum for the MPUHeiko Schocher2016-06-091-0/+73
| | | | | | | | | | | | | | | | | | | | | | | | Enable Spread Spectrum for the MPU by calculating the required values and setting the registers accordingly. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | Merge http://git.denx.de/u-boot-samsungTom Rini2016-06-061-0/+3
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: configs/peach-pi_defconfig configs/peach-pit_defconfig
| * | | exynos: pwm: Add a driver for the exynos5 PWMSimon Glass2016-05-251-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver supports the standard PWM API. There are 5 PWMs. Four are used normally and the last is normally used as a timer. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | | arm/arm64: implement a boot header capabilityAndre Przywara2016-06-061-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some SPL loaders (like Allwinner's boot0, and Broadcom's boot0) require a header before the actual U-Boot binary to both check its validity and to find other data to load. Sometimes this header may only be a few bytes of information, and sometimes this might simply be space that needs to be reserved for a post-processing tool. Introduce a config option to allow assembler preprocessor commands to be inserted into the code at the appropriate location; typical assembler preprocessor commands might be: .space 1000 .word 0x12345678 Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Steve Rae <srae@broadcom.com> Commit Notes: Please note that the current code: start.S (arm64) and vectors.S (arm) already jumps over some portion of data already, so this option basically just increases the size of this region (and the resulting binary). For use with Allwinner's boot0 blob there is a tool called boot0img[1], which fills the header to allow booting A64 based boards. For the Pine64 we need a 1536 byte header (including the branch instruction) at the moment, so we add this to the defconfig. [1] https://github.com/apritzel/pine64/tree/master/tools END Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | armv7: fix order of OMAP die ID printingLadislav Michl2016-06-061-2/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Acked-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
* | | | Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2016-06-061-0/+5
|\ \ \ \
| * | | | ARM64: zynqmp: Extend page_table_sizeMichal Simek2016-06-061-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 0xc000 is not sufficient page table size if dc4 with 4 gems is enabled. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-06-048-2/+229
|\ \ \ \ \ | |/ / / / |/| | | |
| * | | | armv8: fsl-layerscape: Add support of QorIQ LS1012A SoCPrabhakar Kushwaha2016-06-036-0/+136
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. This patch add support of LS1012A SoC along with - Update platform & DDR clock read logic as per SVR - Define MMDC controller register set. - Update LUT base address for PCIe - Avoid L3 platform cache compilation - Update USB address, errata - SerDes table - Added CSU IDs for SDHC2, SAI-1 to SAI-4 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | | armv8: fsl-layerscape: Organize SoC overview at common locationPrabhakar Kushwaha2016-06-033-0/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SoC overviews are getting repeated across board folders. So, Organize SoC overview at common location i.e. fsl-layerscape/doc Also move README.lsch2 and README.lsch3 in same folder. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
OpenPOWER on IntegriCloud