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* aspeed/flash: Add MT25QL01GB chipAdriana Kobylak2019-04-051-0/+14
| | | | | | | | | The MT25QL01GB is a 128MB NOR flash chip planned to be used on a Witherspoon system (AST2500). Signed-off-by: Adriana Kobylak <anoo@us.ibm.com> Tested-by: Adriana Kobylak <anoo@us.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
* aspeed/ast-scu.c: add ast_get_m_pll_clk() for AST_SOC_G5David Thompson2019-04-042-0/+43
| | | | | | | | | | | | | This code change adds the AST_SOC_G5 version of ast_get_m_pll_clk(), which is relevant to AST1520, AST2500, and AST3200 devices. This change properly enables the AST_SOC_G5 logic in print_cpuinfo(), which can be turned on by defining CONFIG_DISPLAY_CPUINFO. Signed-off-by: David Thompson <dthompson@mellanox.com> Reviewed-by: Shravan Ramani <sramani@mellanox.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* arch-aspeed: Make AHBC and SDMC header guards uniqueAndrew Jeffery2018-07-242-4/+4
| | | | | | | | Otherwise we get mysterious missing symbols if we include both those and the ast-{ahbc,sdmc}.h files. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* platform_g5: Disable CONFIG_DDR4_SUPPORT_HYNIXJoel Stanley2018-07-241-1/+1
| | | | | | This maintains the existing behaviour of u-boot on ast2500. Signed-off-by: Joel Stanley <joel@jms.id.au>
* platform_g5: Update to v18Joel Stanley2018-07-121-8/+71
| | | | Signed-off-by: Joel Stanley <joel@jms.id.au>
* platform_g4: Update to v0.62Joel Stanley2018-07-121-2/+10
| | | | Signed-off-by: Joel Stanley <joel@jms.id.au>
* aspeed/flash: fix buffersize of MX6651235F flash chipRobert Lippert2018-02-131-1/+1
| | | | | | | | | The MX66L51235F had a wrong write buffersize of 512 bytes set which causes issues when trying to write an environment block >256 bytes as the SPI chip only "listens" to the last 256 bytes. Signed-off-by: Robert Lippert <rlippert@google.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
* aspeed/timer: move static variables under arch_global_dataCédric Le Goater2017-10-211-2/+4
| | | | | | | | | The timestamp and lastdec variables are under BSS which is a problem as the timer_init() routine is called in the early init phase. Move them under arch_global_data. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
* Revert "ast-g5: deactivate vbar (for qemu)"Cédric Le Goater2017-10-211-1/+1
| | | | | | | | | | | | | | | This reverts commit a0ca4ecbeae4ae9632ebc67bf5318dd2ea09c94f. Support was added to QEMU in : commit 91db4642f868 ("target-arm: Add VBAR support to ARM1176 CPUs") The work around happens to crash the guest when the vector relocation is done, with ignore_memory_transaction_failures=false which is now the default in QEMU. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
* Add MTD support to Aspeed Flash driverAdriana Kobylak2017-08-241-0/+20
| | | | | | | | | | | | Add support to the aspeed flash driver to enable the common mtd layer through CONFIG_FLASH_CFI_MTD. This enables the flash to be used by u-boot mtd drivers including the mtdparts and ubi commands. Signed-off-by: Adriana Kobylak <anoo@linux.vnet.ibm.com> Acked-by: Milton Miller <miltonm@us.ibm.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
* aspeed: Add defines for all watchdogsJoel Stanley2017-06-263-5/+8
| | | | | | | This adds defines for WDT2 (and WDT3 for the ast2500), and renames the existing one to WDT1. Signed-off-by: Joel Stanley <joel@jms.id.au>
* aspeed: Update platform_g5.S to version 16Joel Stanley2017-06-261-10/+250
| | | | | | | | | | 1.[P1] Add margin check/retry for DDR4 Vref training margin. 2.[P1] Add margin check/retry for DDR3/DDR4 read timing training margin. 3.[P2] Add initial sequence for LPC controller 4.[P2] Add initial full-chip reset option 5.[P3] Add 10ms delay after DDR reset Signed-off-by: Joel Stanley <joel@jms.id.au>
* aspeed: Update platform_g5.S to version 15Joel Stanley2017-05-261-51/+266
| | | | | | This is the latest release from Aspeed. Signed-off-by: Joel Stanley <joel@jms.id.au>
* board/aspeed: Add ast-g5 boardJoel Stanley2016-07-271-0/+1
| | | | | | | This adds a Aspeed fifth generation board with defconfigs for a system with NCSI and with a directly attached PHY configuration. Signed-off-by: Joel Stanley <joel@jms.id.au>
* ast-g5: deactivate vbar (for qemu)Cédric Le Goater2016-07-271-1/+1
| | | | | | | | This is work around for the ast2500 qemu guest which does not handle the vbar yet. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
* arm/arm1176: Aspeed start.S hackJoel Stanley2016-07-271-4/+4
| | | | | | This was included by Apseed in their SDK. Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: AST2500: add supportJoel Stanley2016-07-2725-0/+8922
| | | | | | Extracted from ast_sdk.v00.03.21 which is based on u-boot v2013. Signed-off-by: Joel Stanley <joel@jms.id.au>
* armv8: Enable CPUECTLR.SMPEN for coherencyMingkai Hu2016-07-081-0/+8
| | | | | | | | | | | | | | | | For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is set. The SMPEN bit should be set before enabling the data cache. If not enabled, the cache is not coherent with other cores and data corruption could occur. For A57/A72, SMPEN bit enables the processor to receive instruction cache and TLB maintenance operations broadcast from other processors in the cluster. This bit should be set before enabling the caches and MMU, or performing any cache and TLB maintenance operations. Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* arm: Fix setjmp (again)Alexander Graf2016-07-081-1/+3
| | | | | | | | | | | | Commit e677724 (arm: Fix setjmp) added code to fix compilation of the setjmp code path with thumv1. Unfortunately it missed a constraint that the adr instruction can only refer to 4 byte aligned offsets. So this patch adds the required alignment hooks to make compilation work again even when setjmp doesn't happen to be 4 byte aligned. Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-07-071-0/+2
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| * powerpc: mpc85xx: Do not build errata command in SPLMarek Vasut2016-07-051-0/+2
| | | | | | | | | | | | | | | | | | The errata command is useless in SPL, so don't build it. This fixes multiple build failures on PowerPC. Signed-off-by: Marek Vasut <marex@denx.de> Cc: York Sun <york.sun@nxp.com> Fixes: 92623672f9d3 ("fsl: usb: make errata function common for PPC and ARM")
* | video: tegra: Move to using simple-panel and pwm-backlightSimon Glass2016-07-053-72/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have standard drivers for panels and backlights which can do most of the work for us. Move the tegra20 LCD driver over to use those instead of custom code. This patch includes device tree changes for the nvidia boards. I have only been able to test seaboard. If this patch is applied, these boards will also need to be synced with the kernel, and updated to use display-timings: - colibri - medcom-wide - paz00 - tec Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | tegra: dts: Sync tegra20 device tree files with LinuxSimon Glass2016-07-053-73/+2154
|/ | | | | | | | Sync everything except the display panel, which will come in a future patch. One USB port is left disabled since we don't want to support it in U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Merge git://git.denx.de/u-boot-arcTom Rini2016-07-042-2/+4
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| * arc: make global_data.h usable in assembly filesAlexey Brodkin2016-07-041-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently on attempt to use global_data.h in an assembly file following will happen: -------------------->8----------------- ./arch/arc/include/asm/global_data.h: Assembler messages: ./arch/arc/include/asm/global_data.h:11: Error: bad instruction 'struct arch_global_data{' ./arch/arc/include/asm/global_data.h:12: Error: junk at end of line, first unrecognized character is `}' scripts/Makefile.build:316: recipe for target 'arch/arc/lib/start.o' failed -------------------->8----------------- In this change we disable struct arch_global_data in ASM which fixes the issue above. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * arc: Use "-mcpu=archs" instead of deprecated "-marchs" for ARC HSAlexey Brodkin2016-07-041-2/+2
| | | | | | | | | | | | | | | | | | Newer ARC toolchains don't support "-marchs" option any longer. Instead "-mcpu=archs" should be used. What's also important older toiolchains that support ARC HS cores will also happily accept "-mcpu=archs" so that's a very safe move. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | sunxi: Add defconfig and DTS file for Allwinner R16 EVB (Parrot)Quentin Schulz2016-07-022-1/+350
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Parrot Board is an evaluation board with an Allwinner R16 (assumed to be close to an Allwinner A33), 4GB of eMMC, 512MB of RAM, USB host and OTG, a WiFi/Bluetooth combo chip, a micro SD Card reader, 2 controllable buttons, an LVDS port with separated backlight and capacitive touch panel ports, an audio/microphone jack, a camera CSI port, 2 sets of 22 GPIOs and an accelerometer. The DTS file is identical to the one submitted to the upstream kernel. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: Add missing boot_media fields in the SPL headerOlliver Schinagl2016-07-021-0/+2
|/ | | | | | | | | | | Commit b19236fd1 ("sunxi: Increase SPL header size to 64 bytes to avoid code corruption") Added defines for MMC0 and SPI as boot identification. After verifying on an OLinuXino Lime2 with NAND and eMMC, the expected values have been confirmed and added to spl.h Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* ARM: uniphier: add external IRQ setup codeMasahiro Yamada2016-07-022-0/+44
| | | | | | | | I will carry this work-around until it is cared in the kernel. This looks up the AIDET node and sets up a register to handle active low interrupt signals. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: uniphier: add AIDET nodesMasahiro Yamada2016-07-028-0/+40
| | | | | | | The AIDET (ARM Interrupt Detector Add-on Circuit) is a kind of syscon block related with the interrupt controller. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: uniphier: sync Device Trees with upstream LinuxMasahiro Yamada2016-07-0222-138/+99
| | | | | | I periodically sync Device Trees for better maintainability. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: fix typo "talbe"Masahiro Yamada2016-06-301-1/+1
| | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* x86: coreboot: Remove the dummy pch driverBin Meng2016-06-292-27/+0
| | | | | | | | | There is a dummy pch driver in the coreboot directory. This causes drivers of its children fail to function due to empty ops. Remove the whole file since it is no longer needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-06-287-124/+21
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| * armv8: dts: fsl: Remove cpu nodes from Layerscape DTSIsAbhimanyu Saini2016-06-283-105/+0
| | | | | | | | | | | | | | | | | | | | | | | | Currently layescape SoCs are not using cpu nodes. So removing them in favour of compatibly with similar SoCs that have different cores like LS2080A and LS2088A. This has been tested on LS2080AQDS, LS1043ARDB, LS1012ARDB. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: Append "A" in SoC name for ARM based SoCsPrabhakar Kushwaha2016-06-283-16/+16
| | | | | | | | | | | | | | | | | | | | | | Freescale ARMv8 SoC name ends with "A" to represent ARM SoCs. like LS2080A, LS1043A, LS1012A. So append "A" to SoC names. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8/fsl_lsch2: Correct the cores frequency initializationHou Zhiqiang2016-06-241-3/+5
| | | | | | | | | | | | | | | | The register CLKCNCSR controls the frequency of all cores in the same cluster. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | arm: at91: taurus/axm: add DM and DTS supportHeiko Schocher2016-06-263-0/+124
| | | | | | | | | | | | | | | | | | | | add DM and DTS support for the at91 based siemens boards. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> [rebased on current ToT] Signed-off-by: Andreas Bießmann <andreas@biessmann.org>
* | arm: at91: smartweb: add DM and DTS supportHeiko Schocher2016-06-263-1/+116
| | | | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> [rebased on current ToT] Signed-off-by: Andreas Bießmann <andreas@biessmann.org>
* | arm: at91: dts: Bring in dts files for AT91SAM9G20 and SAM9260Heiko Schocher2016-06-264-0/+3012
| | | | | | | | | | | | | | | | | | Add this files from Linux v4.6-rc5 66b8a424d: [workqueue: fix ghost PENDING flag while doing MQ IO] Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Andreas Bießmann <andreas@biessmann.org>
* | corvus DTS / DM supportHeiko Schocher2016-06-263-1/+115
| | | | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> [rebase on current ToT, don't delete gurnard DTB creation] Signed-off-by: Andreas Bießmann <andreas@biessmann.org>
* | arm: at91: add CONFIG_AT91SAM9M10G45Heiko Schocher2016-06-261-12/+14
| | | | | | | | | | | | | | add support for CONFIG_AT91SAM9M10G45. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
* | ARM: at91: Don't invoke spl_boot_device() twiceMarek Vasut2016-06-261-1/+1
| | | | | | | | | | | | | | | | | | | | Since the spl_boot_mode() is now passed the boot device to boot from, make use of it instead of inquiring for the boot device again. This allows board_boot_order() to function correctly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
* | common: Pass the boot device into spl_boot_mode()Marek Vasut2016-06-2614-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPL code already knows which boot device it calls the spl_boot_mode() on, so pass that information into the function. This allows the code of spl_boot_mode() avoid invoking spl_boot_device() again, but it also lets board_boot_order() correctly alter the behavior of the boot process. The later one is important, since in certain cases, it is desired that spl_boot_device() return value be overriden using board_boot_order(). Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> [add newly introduced zynq variant] Signed-aff-by: Andreas Bießmann <andreas@biessmann.org>
* | board/BuR: rename kwb board to brxre1Hannes Schmelzer2016-06-241-3/+3
| | | | | | | | | | | | | | Rename B&R kwb board to brxre1 Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Tom Rini <trini@konsulko.com>
* | board/BuR: rename tseries board to brppt1Hannes Schmelzer2016-06-241-3/+3
| | | | | | | | | | | | | | Rename B&R tseries board to brppt1 Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm: bcm235xx: update clock frameworkSteve Rae2016-06-241-5/+5
| | | | | | | | | | | | | | | | The handling of the "usage counter" is incorrect, and the clock should only be disabled when transitioning from 1 to 0. Reported-by: Chris Brand <chris.brand@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
* | arm: bcm235xx: fix kps ccuChris Brand2016-06-241-5/+1
| | | | | | | | | | | | | | The Kona Peripheral Slave CCU has 4 policy mask registers, not 8. Signed-off-by: Chris Brand <chris.brand@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
* | arm: bcm235xx: implement the boot0 hook codeSteve Rae2016-06-241-0/+15
| | | | | | | | | | | | Choose the Kconfig boot0 hook option and implement the required code. Signed-off-by: Steve Rae <srae@broadcom.com>
* | ARM: armv7: refactor Makefile slightlyMasahiro Yamada2016-06-241-9/+2
| | | | | | | | | | | | Use Kbuild standard style where possible. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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