summaryrefslogtreecommitdiffstats
path: root/src/usr/targeting/common/xmltohb/simics_AXONE.system.xml
Commit message (Expand)AuthorAgeFilesLines
* Correct target hiearchy in axone system xmlChristian Geddes2020-01-101-2/+2
* Update DIMM mux_select to match their OCMB counterpartsChristian Geddes2019-09-051-32/+16
* Axone 2-Proc Standalone Sim EnablementBill Hoffa2019-08-301-105/+11787
* OR mux select with the "enable" bit 0b1000 when making selectionChristian Geddes2019-08-011-24/+24
* Force sbe update loop if a change in OMI freq is detectedChristian Geddes2019-07-171-1/+5
* Add HCDB Support for eeprom cache processChristian Geddes2019-06-261-16/+62
* Update DIMM's 0-8 EEPROM_VPD_PRIMARY_INFO to match the corresponding OCMBsChristian Geddes2019-06-111-38/+38
* Update non-present dimm/ocmb i2c attributesChristian Geddes2019-06-101-102/+113
* Document Axone NPU configurationDan Crowell2019-05-291-257/+214
* Clean up traces seen during Axone IPLsChristian Geddes2019-05-291-1/+1
* Combine 'generic' and 'explorer' OCMB chip targetsMike Baiocchi2019-05-161-16/+16
* Targeting updates for EEPROM content typeMatthew Raybuck2019-05-091-1/+36
* Update simbuild for axone simics bringupGlenn Miles2019-05-071-9/+9
* Set i2c slave's port correctly in Axone XML for OCMB targetsChristian Geddes2019-05-071-34/+50
* Add call to p9a_omi_io_dccal in istep 12.6Christian Geddes2019-05-011-0/+64
* Add FAPI_POS and account for 4 possible PMIC targetsMatt Derksen2019-04-241-81/+133
* Add new PMIC target for AxoneMatt Derksen2019-04-181-2/+726
* Update OCMB 9-15 to have valid i2c and eeprom infoMatthew Raybuck2019-04-181-36/+148
* Validate OMI INBAND BAR offset attributes against calculated valuesChristian Geddes2019-04-181-1/+11
* Update MAX_ALLOWED_DIMM_FREQ to support 3200 MHzChristian Geddes2019-04-101-0/+4
* Re-order i2c properties in Axone simics XML to align closer with simChristian Geddes2019-04-101-49/+49
* Set ATTR_MSS_INTERLEAVE_ENABLE to be 0xAF to allow all grouping sizesChristian Geddes2019-04-031-1/+1
* Set REL_POS to 0 on all DIMM target in simics AxoneChristian Geddes2019-04-021-0/+64
* Set MUX i2c slave port to be 1Christian Geddes2019-03-221-1/+1
* Set MAX_COMPUTE_NODES attribute so TOD code gets setup correctlyChristian Geddes2019-03-171-0/+4
* Allow single dimm configurations in AxoneChristian Geddes2019-03-171-1/+1
* Updates to testcases for AxoneDan Crowell2019-03-071-2/+2
* Set early test case IPL step to be 14.7 in Axone simicsChristian Geddes2019-03-061-1/+1
* Method to execute testcases early in the bootDan Crowell2019-02-281-0/+4
* Set simics xml to match simics model for OCMB port numberingChristian Geddes2019-02-151-7/+7
* Add EEPROM caching device opChristian Geddes2019-02-131-34/+174
* Add call to p9a_ocmb_enable to istep 10.4Christian Geddes2019-02-111-0/+64
* Set the I2C MUX bus selector in the i2cPresence functionRoland Veloz2019-01-301-8/+8
* Set TPM model to be the x75 nuvoton for axone simicsChristian Geddes2019-01-241-0/+4
* Replace attribute I2C_MUX_INFO with attribute FAPI_I2C_CONTROL_INFORoland Veloz2019-01-151-10/+1
* Fix EEPROM_VPD_PRIMARY_INFO attribute on proc targ in axone sim XMLChristian Geddes2019-01-141-4/+8
* Add presence detection for i2c mux targetsChristian Geddes2019-01-111-0/+9
* Real OCMB presence detection support for Axone simicsChristian Geddes2019-01-081-16/+354
* HB Axone simics model changes to support DDIMM SPD i2c accessRoland Veloz2018-12-181-2/+223
* Fill in remaining dimms for simics_AXONE.system.xmlChristian Geddes2018-12-181-7/+247
* Add VPD_REC_NUM defaults for OCMB chips in Axone system xml for simChristian Geddes2018-12-171-0/+64
* Axone Simics Updates -- Finds Functional Master ProcBill Hoffa2018-12-141-6/+6
* Inband MMIO access to OCMBRick Ward2018-12-131-0/+83
* Default ASYNC_NEST_FREQ_MHZ to be 0xFFFF for Axone simics xmlChristian Geddes2018-12-101-0/+4
* Driver changes to support i2c muxRoland Veloz2018-12-061-1/+1
* Set FSIMASTER attributes to correct valuesChristian Geddes2018-11-271-3/+3
* Define Parent/Child Relationship for OMIC/OMI targetsChristian Geddes2018-11-271-0/+64
* Fix CAPP target XML in Axone simics xml fileChristian Geddes2018-11-201-2/+2
* Update axone simics xml to use correct chiplet id for MC1 chipletChristian Geddes2018-11-151-3/+3
* Add the PERVASIVE (PERV) Target Instances to Axone Simics XMLBill Hoffa2018-10-261-0/+2505
OpenPOWER on IntegriCloud