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| author | Christian Geddes <crgeddes@us.ibm.com> | 2019-01-09 12:51:38 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-01-14 16:47:51 -0600 |
| commit | 5ccb0c4605c0f30a18a509fc0f686f994ae651d8 (patch) | |
| tree | 95e7aab79200a38541d2fd7540e4ea00028f4f27 /src/usr/targeting/common/xmltohb/simics_AXONE.system.xml | |
| parent | ac15fd763d3ef2968adcb4140f1f930f29ba6ecb (diff) | |
| download | talos-hostboot-5ccb0c4605c0f30a18a509fc0f686f994ae651d8.tar.gz talos-hostboot-5ccb0c4605c0f30a18a509fc0f686f994ae651d8.zip | |
Fix EEPROM_VPD_PRIMARY_INFO attribute on proc targ in axone sim XML
Up until this point in P9 systems this attribute has had the
maxMemorySizeKB = 0x80 (128 KB) and the chipCount = 0x02. While
this is partially true, hostboot should never access the 2nd 64 KB
chip. The MVPD is completely stored in the first 64 KB chip. This
commit intentionally does not fix previous system XMLs but it might
be worth investigating. MRW is still supplying the old 0x80, 0x02 values
for Nimbus/Cumuls system so it was decided to leave old values in our
sim xmls for those systems.
RTC: 196805
Change-Id: Ibec7412359b6cda24a255ec612a5774a7ed3ac30
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70259
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Roland Veloz <rveloz@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/usr/targeting/common/xmltohb/simics_AXONE.system.xml')
| -rw-r--r-- | src/usr/targeting/common/xmltohb/simics_AXONE.system.xml | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/src/usr/targeting/common/xmltohb/simics_AXONE.system.xml b/src/usr/targeting/common/xmltohb/simics_AXONE.system.xml index 662e283ea..46dea6902 100644 --- a/src/usr/targeting/common/xmltohb/simics_AXONE.system.xml +++ b/src/usr/targeting/common/xmltohb/simics_AXONE.system.xml @@ -445,11 +445,13 @@ <id>EEPROM_VPD_BACKUP_INFO</id> <default> <field><id>byteAddrOffset</id><value>0x02</value></field> - <field><id>chipCount</id><value>0x02</value></field> <field><id>devAddr</id><value>0xA0</value></field> <field><id>engine</id><value>1</value></field> <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> - <field><id>maxMemorySizeKB</id><value>0x80</value></field> + <!-- Note: that there is actually two 64KB chips associated with the MVPD SEEPROM + but Hostboot should never access the second chip --> + <field><id>chipCount</id><value>0x01</value></field> + <field><id>maxMemorySizeKB</id><value>0x40</value></field> <field><id>port</id><value>2</value></field> <field><id>writeCycleTime</id><value>0x0A</value></field> <field><id>writePageSize</id><value>0x80</value></field> @@ -459,11 +461,13 @@ <id>EEPROM_VPD_PRIMARY_INFO</id> <default> <field><id>byteAddrOffset</id><value>0x02</value></field> - <field><id>chipCount</id><value>0x02</value></field> <field><id>devAddr</id><value>0xA0</value></field> <field><id>engine</id><value>1</value></field> <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> - <field><id>maxMemorySizeKB</id><value>0x80</value></field> + <!-- Note: that there is actually two 64KB chips associated with the MVPD SEEPROM + but Hostboot should never access the second chip --> + <field><id>chipCount</id><value>0x01</value></field> + <field><id>maxMemorySizeKB</id><value>0x40</value></field> <field><id>port</id><value>0</value></field> <field><id>writeCycleTime</id><value>0x0A</value></field> <field><id>writePageSize</id><value>0x80</value></field> |
