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* [InstCombine] new testcases for OverflowingBinaryOperators and ↵Omer Paparo Bivas2018-05-011-0/+1149
| | | | | | | | | PossiblyExactOperators transformations; NFC instcombine should transform the relevant cases if the OverflowingBinaryOperator/PossiblyExactOperator can be proven to be safe. Change-Id: I7aec62a31a894e465e00eb06aed80c3ea0c9dd45 llvm-svn: 331265
* [X86] Split WriteFShuffle into XMM and YMM/ZMM scheduler classesSimon Pilgrim2018-05-011-74/+74
| | | | | | Removes more WriteFShuffle InstRW overrides llvm-svn: 331264
* [AArch64][SVE] Asm: Support for contiguous ST1 (scalar+scalar) store ↵Sander de Smalen2018-05-018-0/+171
| | | | | | | | | | | | instructions. Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D46121 llvm-svn: 331260
* Reland r331175: "[mips] Fix the predicates of jump and branch and link ↵Simon Dardis2018-05-011-1/+2
| | | | | | | | | | | | | | | | instructions" The previous version of this patch restricted the 'jal' instruction to MIPS and microMIPSr3. microMIPS32r6 does not have this instruction and instead uses jal as an alias for balc. Original commit message: > Reviewers: smaksimovic, atanasyan, abeserminji > > Differential Revision: https://reviews.llvm.org/D46114 > llvm-svn: 331259
* [X86] Split WriteVecLogic into XMM and YMM/ZMM scheduler classesSimon Pilgrim2018-05-012-5/+5
| | | | | | This removes all the WriteVecLogic InstRW overrides. llvm-svn: 331258
* [InstCombine] Adjusting bswap pattern matching to hold for And/Shift mixed caseOmer Paparo Bivas2018-05-011-5/+2
| | | | | | | Differential Revision: https://reviews.llvm.org/D45731 Change-Id: I85d4226504e954933c41598327c91b2d08192a9d llvm-svn: 331257
* [X86] Correct spill slot size.Andrea Di Biagio2018-05-011-0/+68
| | | | | | | | | | | | | | | This patch fixes a bug introduced by revision 330778 (originally reviewed at: https://reviews.llvm.org/D44782), where function isFrameLoadOpcode returned the wrong number of bytes read for opcodes VMOVSSrm and VMOVSDrm. This corrects that mistake, and extends the regression test to catch cases where the dead stores should be removed. Patch by Jeremy Morse. Differential Revision: https://reviews.llvm.org/D46256 llvm-svn: 331252
* [X86] movdiri and movdir64b instructionsGabor Buella2018-05-018-0/+138
| | | | | | | | | | Reviewers: spatel, craig.topper, RKSimon Reviewed By: craig.topper, RKSimon Differential Revision: https://reviews.llvm.org/D45983 llvm-svn: 331248
* [X86] Remove 'opaque ptr' from the intel syntax parser and printer.Craig Topper2018-05-013-9/+9
| | | | | | | | Previously for instructions like fxsave we would print "opaque ptr" as part of the memory operand. Now we print nothing. We also no longer accept "opaque ptr" in the parser. We still accept any size to be specified for these instructions, but we may want to consider only parsing when no explicit size is specified. This what gas does. llvm-svn: 331243
* Temporarily revert "[DEBUG] Initial adaptation of NVPTX target for debug ↵Eric Christopher2018-05-014-8928/+28
| | | | | | | | | | | | | | | | | info emission." This appears to have some issues associated with the file directive output causing multiple global symbols with the name "file" to be emitted into a startup section. I'm investigating more specific causes and working with the original author. This reverts commit r330271. Also Revert "[DEBUGINFO, NVPTX] Add the test for the debug info of the local" This reverts commit r330592 and the follow up of 330779 as the testcase is dependent upon r330271. llvm-svn: 331237
* [InstCombine] fix test to restore intentSanjay Patel2018-04-301-3/+2
| | | | | | | | | This test had values that differed in only in capitalization, and that causes problems for the auto-generating check line script. So I changed that in rL331226, but I accidentally forgot to change a subsequent use of a param. llvm-svn: 331228
* [InstCombine] add tests, update checks; NFCSanjay Patel2018-04-301-86/+120
| | | | llvm-svn: 331226
* [LivePhysRegs] Remove registers clobbered by regmasks from the live setKrzysztof Parzyszek2018-04-301-0/+39
| | | | | | | | Dead defs were being removed from the live set (in stepForward), but registers clobbered by regmasks weren't (more specifically, they were actually removed by removeRegsInMask, but then they were added back in). llvm-svn: 331219
* [MC] Change AsmParser to leverage Assembler during evaluationNirav Dave2018-04-304-2/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | Teach AsmParser to check with Assembler for when evaluating constant expressions. This improves the handing of preprocessor expressions that must be resolved at parse time. This idiom can be found as assembling-time assertion checks in source-level assemblers. Note that this relies on the MCStreamer to keep sufficient tabs on Section / Fragment information which the MCAsmStreamer does not. As a result the textual output may fail where the equivalent object generation would pass. This can most easily be resolved by folding the MCAsmStreamer and MCObjectStreamer together which is planned for in a separate patch. Currently, this feature is only enabled for assembly input, keeping IR compilation consistent between assembly and object generation. Reviewers: echristo, rnk, probinson, espindola, peter.smith Reviewed By: peter.smith Subscribers: eraman, peter.smith, arichardson, jyknight, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D45164 llvm-svn: 331218
* AMDGPU: Add Vega12 and Vega20Matt Arsenault2018-04-3020-224/+1718
| | | | | | | | Changes by Matt Arsenault Konstantin Zhuravlyov llvm-svn: 331215
* [MIR] Reset unique MBB numbering in MachineFunction::reset()Roman Tereshin2018-04-301-2/+7
| | | | | | | | | | | | | | No need to waste space nor number MBBs differently if MF gets recreated. Reviewers: qcolombet, stoklund, t.p.northover, bogner, javed.absar Reviewed By: qcolombet Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46078 llvm-svn: 331213
* [DAGCombiner] rename function attribute for disabling ftrunc transformSanjay Patel2018-04-301-4/+3
| | | | | | | | | | This is the matching name change for the Clang patch at: D46236 rL331209 Differential Revision: https://reviews.llvm.org/D46237 llvm-svn: 331210
* [InstCombine] Unfold masked merge with constant maskRoman Lebedev2018-04-302-69/+65
| | | | | | | | | | | | | | | | | Summary: As discussed in D45733, we want to do this in InstCombine. https://rise4fun.com/Alive/LGk Reviewers: spatel, craig.topper Reviewed By: spatel Subscribers: chandlerc, xbolva00, llvm-commits Differential Revision: https://reviews.llvm.org/D45867 llvm-svn: 331205
* [InstCombine][NFC] Add tests for unfolding masked merge with constant maskRoman Lebedev2018-04-302-0/+643
| | | | | | | | Summary: As discussed in D45733, we want to do this in InstCombine. Differential Revision: https://reviews.llvm.org/D45866 llvm-svn: 331204
* [SystemZ] Handle SADDO et.al. and ADD/SUBCARRYUlrich Weigand2018-04-3043-2/+10404
| | | | | | | | | | | | | | | | This provides an optimized implementation of SADDO/SSUBO/UADDO/USUBO as well as ADDCARRY/SUBCARRY on top of the new CC implementation. In particular, multi-word arithmetic now uses UADDO/ADDCARRY instead of the old ADDC/ADDE logic, which means we no longer need to use "glue" links for those instructions. This also allows making full use of the memory-based instructions like ALSI, which couldn't be recognized due to limitations in the DAG matcher previously. Also, the llvm.sadd.with.overflow et.al. intrinsincs now expand to directly using the ADD instructions and checking for a CC 3 result. llvm-svn: 331203
* [SystemZ] Do not use glue to represent condition code dependenciesUlrich Weigand2018-04-304-7/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, an instruction setting the condition code is linked to the instruction using the condition code via a "glue" link in the SelectionDAG. This has a number of drawbacks; in particular, it means the same CC cannot be used by multiple users. It also makes it more difficult to efficiently implement SADDO et. al. This patch changes the back-end to represent CC dependencies as normal values during SelectionDAG matching, along the lines of how this is handled in the X86 back-end already. In addition to the core mechanics of updating all relevant patterns, this requires a number of additional changes: - We now need to be able to spill/restore a CC value into a GPR if necessary. This means providing a copyPhysReg implementation for moves involving CC, and defining getCrossCopyRegClass. - Since we still prefer to avoid such spills, we provide an override for IsProfitableToFold to avoid creating a merged LOAD / ICMP if this would result in multiple users of the CC. - combineCCMask no longer requires a single CC user, and no longer need to be careful about preventing invalid glue/chain cycles. - emitSelect needs to be more careful in marking CC live-in to the basic block it generates. Also, we can now optimize the case of multiple subsequent selects with the same condition just like X86 does. llvm-svn: 331202
* Fix infinite loop after r331115Daniel Sanders2018-04-301-0/+61
| | | | | | | | There are two separate fixes here: * The lowering code for non-extending loads should report UnableToLegalize instead of emitting the same instruction. * The target should not be requesting lowering of non-extending loads. llvm-svn: 331201
* [DebugInfo] Prevent infinite recursion for malformed DWARFJonas Devlieghere2018-04-301-0/+296
| | | | | | | | | | | This prevents infinite recursion in DWARFDie::findRecursively for malformed DWARF where a DIE references itself. This fixes PR36257. Differential revision: https://reviews.llvm.org/D43092 llvm-svn: 331200
* [SLPVectorizer] Debug info shouldn't impact spill cost computation.Davide Italiano2018-04-301-0/+93
| | | | | | | | | | <rdar://problem/39794738> (Also, PR32761). Differential Revision: https://reviews.llvm.org/D46199 llvm-svn: 331199
* [llvm-mca] Correctly handle zero-latency stores that consume pipeline resources.Andrea Di Biagio2018-04-301-0/+44
| | | | | | | | | | | | | | | | This fixes PR37293. We can have scheduling classes with no write latency entries, that still consume processor resources. We don't want to treat those instructions as zero-latency instructions; they still have to be issued to the underlying pipelines, so they still consume resource cycles. This is likely to be a regression which I have accidentally introduced at revision 330807. Now, if an instruction has a non-empty set of write processor resources, we conservatively treat it as a normal (i.e. non zero-latency) instruction. llvm-svn: 331193
* [SystemZ] Improve handling of Select pseudo-instructionsUlrich Weigand2018-04-301-6/+10
| | | | | | | | | | | | | | | If we have LOCR instructions, select them directly from SelectionDAG instead of first going through a pseudo instruction and then using the custom inserter to emit the LOCR. Provide Select pseudo-instructions for VR32/VR64 if we have vector instructions, to avoid having to go through the first 16 FPRs unnecessarily. If we do not have LOCFHR, prefer using LOCR followed by a move over a conditional branch. llvm-svn: 331191
* [BranchFolding] Salvage DBG_VALUE instructions from empty blocksBjorn Pettersson2018-04-301-0/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch will introduce copying of DBG_VALUE instructions from an otherwise empty basic block to predecessor/successor blocks in case the empty block is eliminated/bypassed. It is currently only done in one identified situation in the BranchFolding pass, before optimizing on empty block. It can be seen as a light variant of the propagation done by the LiveDebugValues pass, which unfortunately is executed after the BranchFolding pass. We only propagate (copy) DBG_VALUE instructions in a limited number of situations: a) If the empty BB is the only predecessor of a successor we can copy the DBG_VALUE instruction to the beginning of the successor (because the DBG_VALUE instruction is always part of the flow between the blocks). b) If the empty BB is the only successor of a predecessor we can copy the DBG_VALUE instruction to the end of the predecessor (because the DBG_VALUE instruction is always part of the flow between the blocks). In this case we add the DBG_VALUE just before the first terminator (assuming that the terminators do not impact the DBG_VALUE). A future solution, to handle more situations, could perhaps be to run the LiveDebugValues pass before branch folding? This fix is related to PR37234. It is expected to resolve the problem seen, when applied together with the fix in SelectionDAG from here: https://reviews.llvm.org/D46129 Reviewers: #debug-info, aprantl, rnk Reviewed By: #debug-info, aprantl Subscribers: ormris, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D46184 llvm-svn: 331183
* [SelectionDAG] Improve selection of DBG_VALUE using a PHI node resultBjorn Pettersson2018-04-303-3/+355
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When building the selection DAG at ISel all PHI nodes are selected and lowered to Machine Instruction PHI nodes before we start to create any SDNodes. So there are no SDNodes for values produced by the PHI nodes. In the past when selecting a dbg.value intrinsic that uses the value produced by a PHI node we have been handling such dbg.value intrinsics as "dangling debug info". I.e. we have not created a SDDbgValue node directly, because there is no existing SDNode for the PHI result, instead we deferred the creationg of a SDDbgValue until we found the first use of the PHI result. The old solution had a couple of flaws. The position of the selected DBG_VALUE instruction would end up quite late in a basic block, and for example not directly after the PHI node as in the LLVM IR input. And in case there were no use at all in the basic block the dbg.value could be dropped completely. This patch introduces a new VREG kind of SDDbgValue nodes. It is similar to a SDNODE kind of node, but it refers directly to a virtual register and not a SDNode. When we do selection for a dbg.value that is using the result of a PHI node we can do a lookup of the virtual register directly (as it already is determined for the PHI node) and create a SDDbgValue node immediately instead of delaying the selection until we find a use. This should fix a problem with losing debug info at ISel as seen in PR37234 (https://bugs.llvm.org/show_bug.cgi?id=37234). It does not resolve PR37234 completely, because the debug info is dropped later on in the BranchFolder (see D46184). Reviewers: #debug-info, aprantl Reviewed By: #debug-info, aprantl Subscribers: rnk, gbedwell, aprantl, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D46129 llvm-svn: 331182
* Revert "[mips] Fix the predicates of jump and branch and link instructions"Simon Dardis2018-04-301-2/+1
| | | | | | | | That commit broke one of the LLD builders, reverting while I investigate. This patch reverts r331175. llvm-svn: 331178
* [mips] Fix the predicates of jump and branch and link instructionsSimon Dardis2018-04-301-1/+2
| | | | | | | | Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D46114 llvm-svn: 331175
* [llvm-mca] Regenerate test Atom/resources-sse3.s. NFCAndrea Di Biagio2018-04-301-47/+41
| | | | | | Before this change, it wrongly specified -mcpu=slm instead of -mcpu=atom. llvm-svn: 331170
* [llvm-mca] Support for in-order CPU for -instruction-tables testing.Andrea Di Biagio2018-04-307-0/+3787
| | | | | | | | | Added Intel Atom tests to verify that the tool correctly generates instruction tables even if the CPU is in-order. Fixes PR37282. llvm-svn: 331169
* [mips] Fix microMIPS loads and stores.Simon Dardis2018-04-304-8/+1524
| | | | | | | | | | | Previously these instructions were unselectable and instead were generated through the instruction mapping tables. Reviewers: atanasyan, smaksimovic, abeserminji Differential Revision: https://reviews.llvm.org/D46055 llvm-svn: 331165
* [AArch64][SVE] Asm: Improve diagnostics for gather loads.Sander de Smalen2018-04-3010-36/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch extends the 'isSVEVectorRegWithShiftExtend' function to improve diagnostics for SVE's gather load (scalar + vector) addressing modes. Instead of always suggesting the 'unscaled' addressing mode, the use of DiagnosticPredicate enables a more specific error message in the context where the scaling is incorrect. For example: ld1h z0.d, p0/z, [x0, z0.d, lsl #2] ^ shift amount should be '1' Instead of suggesting the packed, unscaled addressing mode: expected 'z[0..31].d, (uxtw|sxtw)' the assembler now suggests using the proper scaling: expected 'z[0..31].d, (lsl|uxtw|sxtw) #1' Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D46124 llvm-svn: 331162
* [X86] Add a Requires<[In64BitMode]> to FARJMP64Craig Topper2018-04-302-1/+4
| | | | | | Otherwise we can try to assemble it in 32-bit mode and throw an assert in the encoder. llvm-svn: 331161
* [X86] Remove support for accepting 'fnstsw %eax' and 'fnstsw %al'.Craig Topper2018-04-302-8/+0
| | | | | | I assume this was done because gas accepted it at one point, but current versions of gas don't. llvm-svn: 331154
* [X86] Make 64-bit sysret/sysexit not ambiguous in Intel assembly syntax.Craig Topper2018-04-291-0/+9
| | | | | | This also makes it default to the 32-bit non REX.W version in 64-bit mode. This seems to be more consistent with gas. llvm-svn: 331149
* [AArch64][SVE] Asm: Support for gather LD1/LDFF1 (vector + imm) load ↵Sander de Smalen2018-04-2928-0/+864
| | | | | | | | | | | | instructions. Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D46120 llvm-svn: 331145
* [llvm-mca][X86] Add BT resource tests to all modelsSimon Pilgrim2018-04-298-8/+1184
| | | | llvm-svn: 331144
* [llvm-mca][X86] Add add/adc + sub/sbb resource tests to all modelsSimon Pilgrim2018-04-298-8/+3016
| | | | llvm-svn: 331140
* [X86] Add suffixes to the LGDT/LIDT/SGDT/SIDT mnemonics in Intel syntax. Add ↵Craig Topper2018-04-292-4/+22
| | | | | | | | | | aliases based on 16/32-bit mode to choose the default. This allows the instruction selection to follow mode in Intel syntax. And allows a suffix to be used to change size. This matches gas behavior from what I could tell. llvm-svn: 331138
* [X86] Remove SLDT64m instruction.Craig Topper2018-04-292-23/+11
| | | | | | | | It doesn't really exist. The instruction always writes 16-bits of memory. Putting a REX.w on it won't change anything. While I was touching the encoding tests to remove it, I added some other missing register form test cases. llvm-svn: 331135
* [LLVM-C] Add DIBuilder bindings to create import declarationsRobert Widmann2018-04-281-25/+29
| | | | | | | | | | | | | | Summary: Add bindings to create import declarations for modules, functions, types, and other entities. This wraps the conveniences available in the existing DIBuilder API, but these seem C++-specific. Reviewers: whitequark, harlanhaskins, deadalnix Reviewed By: whitequark Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46167 llvm-svn: 331123
* [globalisel][legalizerinfo] Introduce dedicated extending loads and add ↵Daniel Sanders2018-04-283-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | lowerings for them Summary: Previously, a extending load was represented at (G_*EXT (G_LOAD x)). This had a few drawbacks: * G_LOAD had to be legal for all sizes you could extend from, even if registers didn't naturally hold those sizes. * All sizes you could extend from had to be allocatable just in case the extend went missing (e.g. by optimization). * At minimum, G_*EXT and G_TRUNC had to be legal for these sizes. As we improve optimization of extends and truncates, this legality requirement would spread without considerable care w.r.t when certain combines were permitted. * The SelectionDAG importer required some ugly and fragile pattern rewriting to translate patterns into this style. This patch begins changing the representation to: * (G_[SZ]EXTLOAD x) * (G_LOAD x) any-extends when MMO.getSize() * 8 < ResultTy.getSizeInBits() which resolves these issues by allowing targets to work entirely in their native register sizes, and by having a more direct translation from SelectionDAG patterns. This patch introduces the new generic instructions and new variation on G_LOAD and adds lowering for them to convert back to the existing representations. Depends on D45466 Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, aemerson, javed.absar Reviewed By: aemerson Subscribers: aemerson, kristof.beyls, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D45540 llvm-svn: 331115
* [InstCombine] Canonicalize variable mask in masked mergeRoman Lebedev2018-04-282-93/+62
| | | | | | | | | | | | | | | | | | | Summary: Masked merge has a pattern of: `((x ^ y) & M) ^ y`. But, there is no difference between `((x ^ y) & M) ^ y` and `((x ^ y) & ~M) ^ x`, We should canonicalize the pattern to non-inverted mask. https://rise4fun.com/Alive/Yol Reviewers: spatel, craig.topper Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45664 llvm-svn: 331112
* [InstCombine][NFC] Add tests for variable mask canonicalization in masked mergeRoman Lebedev2018-04-282-0/+770
| | | | | | | | | | | Summary: Masked merge has a pattern of: `((x ^ y) & M) ^ y`. But, there is no difference between `((x ^ y) & M) ^ y` and `((x ^ y) & ~M) ^ x`, We should canonicalize the pattern to non-inverted mask. Differential Revision: https://reviews.llvm.org/D45663 llvm-svn: 331111
* [llvm-mca][X86] Add double shift resource tests to all relevant modelsSimon Pilgrim2018-04-288-8/+608
| | | | llvm-svn: 331109
* [llvm-mca][X86] Add shift/rotate resource tests to all relevant modelsSimon Pilgrim2018-04-288-0/+4386
| | | | | | I intend to add further instruction tests to the resources-x86_64.s test file as required, but this initial commit is to help remove a load of unnecessary InstRW overrides in a future patch llvm-svn: 331108
* [X86] Remove REX.W from 64-bit mode BND instructions.Craig Topper2018-04-281-6/+6
| | | | | | As far as I can tell from the docs, the instructions are automatically 64-bit in 64-bit mode. We don't need REX.W. llvm-svn: 331102
* [X86] Rename BNDMOV instructions and hide redundant instruction encoding ↵Craig Topper2018-04-281-1/+1
| | | | | | | | | | | | from the assembler. Favor the 0x1a encoding for register/register move to match gas. The instructions used RM and MR in their name along with rr/rm/mr at the end. To make more consistent with other instructions remove the RM/MR and use rr/rm/mr/rr_REV. Hide the _REV encoding from the assembler but leave it for the disassembler. llvm-svn: 331101
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