[globalisel][legalizerinfo] Introduce dedicated extending loads and add lowerings for them

Summary:
Previously, a extending load was represented at (G_*EXT (G_LOAD x)).
This had a few drawbacks:
* G_LOAD had to be legal for all sizes you could extend from, even if
  registers didn't naturally hold those sizes.
* All sizes you could extend from had to be allocatable just in case the
  extend went missing (e.g. by optimization).
* At minimum, G_*EXT and G_TRUNC had to be legal for these sizes. As we
  improve optimization of extends and truncates, this legality requirement
  would spread without considerable care w.r.t when certain combines were
  permitted.
* The SelectionDAG importer required some ugly and fragile pattern
  rewriting to translate patterns into this style.

This patch begins changing the representation to:
* (G_[SZ]EXTLOAD x)
* (G_LOAD x) any-extends when MMO.getSize() * 8 < ResultTy.getSizeInBits()
which resolves these issues by allowing targets to work entirely in their
native register sizes, and by having a more direct translation from
SelectionDAG patterns.

This patch introduces the new generic instructions and new variation on
G_LOAD and adds lowering for them to convert back to the existing
representations.

Depends on D45466

Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, aemerson, javed.absar

Reviewed By: aemerson

Subscribers: aemerson, kristof.beyls, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D45540

llvm-svn: 331115

3 files changed, 75 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extload.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extload.mir
new file mode 100644
index 00000000000..c96788ac9b9
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extload.mir
@@ -0,0 +1,25 @@
+# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - -verify-machineinstrs | FileCheck %s
+
+--- |
+  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+  target triple = "aarch64--"
+  define void @test_extload(i8* %addr) {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_extload
+body: |
+  bb.0.entry:
+    liveins: $x0
+    ; CHECK-LABEL: name: test_extload
+    ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
+    ; CHECK: [[T1:%[0-9]+]]:_(s8) = G_LOAD [[T0]](p0) :: (load 1 from %ir.addr)
+    ; CHECK: [[T2:%[0-9]+]]:_(s32) = G_ANYEXT [[T1]](s8)
+    ; CHECK: $w0 = COPY [[T2]](s32)
+    %0:_(p0) = COPY $x0
+    %1:_(s32) = G_LOAD %0 :: (load 1 from %ir.addr)
+    $w0 = COPY %1
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sextload.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sextload.mir
new file mode 100644
index 00000000000..64dab815445
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sextload.mir
@@ -0,0 +1,25 @@
+# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - -verify-machineinstrs | FileCheck %s
+
+--- |
+  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+  target triple = "aarch64--"
+  define void @test_zextload(i8* %addr) {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_zextload
+body: |
+  bb.0.entry:
+    liveins: $x0
+    ; CHECK-LABEL: name: test_zextload
+    ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
+    ; CHECK: [[T1:%[0-9]+]]:_(s8) = G_LOAD [[T0]](p0) :: (load 1 from %ir.addr)
+    ; CHECK: [[T2:%[0-9]+]]:_(s32) = G_SEXT [[T1]](s8)
+    ; CHECK: $w0 = COPY [[T2]](s32)
+    %0:_(p0) = COPY $x0
+    %1:_(s32) = G_SEXTLOAD %0 :: (load 1 from %ir.addr)
+    $w0 = COPY %1
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-zextload.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-zextload.mir
new file mode 100644
index 00000000000..42bfb2dfb84
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-zextload.mir
@@ -0,0 +1,25 @@
+# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - -verify-machineinstrs | FileCheck %s
+
+--- |
+  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+  target triple = "aarch64--"
+  define void @test_sextload(i8* %addr) {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_sextload
+body: |
+  bb.0.entry:
+    liveins: $x0
+    ; CHECK-LABEL: name: test_sextload
+    ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
+    ; CHECK: [[T1:%[0-9]+]]:_(s8) = G_LOAD [[T0]](p0) :: (load 1 from %ir.addr)
+    ; CHECK: [[T2:%[0-9]+]]:_(s32) = G_ZEXT [[T1]](s8)
+    ; CHECK: $w0 = COPY [[T2]](s32)
+    %0:_(p0) = COPY $x0
+    %1:_(s32) = G_ZEXTLOAD %0 :: (load 1 from %ir.addr)
+    $w0 = COPY %1
+...