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| author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2018-04-30 15:49:27 +0000 |
|---|---|---|
| committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2018-04-30 15:49:27 +0000 |
| commit | fb56686cd344cab8f0bbc369f1ea1b55ab57f5bf (patch) | |
| tree | a7341e80e90d183e7db5761b614477a26b3ab18a /llvm/test | |
| parent | da750079fac2d9fbf7c68196fe1982b694ddfca6 (diff) | |
| download | bcm5719-llvm-fb56686cd344cab8f0bbc369f1ea1b55ab57f5bf.tar.gz bcm5719-llvm-fb56686cd344cab8f0bbc369f1ea1b55ab57f5bf.zip | |
[SystemZ] Improve handling of Select pseudo-instructions
If we have LOCR instructions, select them directly from SelectionDAG
instead of first going through a pseudo instruction and then using
the custom inserter to emit the LOCR.
Provide Select pseudo-instructions for VR32/VR64 if we have vector
instructions, to avoid having to go through the first 16 FPRs
unnecessarily.
If we do not have LOCFHR, prefer using LOCR followed by a move
over a conditional branch.
llvm-svn: 331191
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/SystemZ/asm-18.ll | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/SystemZ/asm-18.ll b/llvm/test/CodeGen/SystemZ/asm-18.ll index 7909253d188..f7be9b45eb6 100644 --- a/llvm/test/CodeGen/SystemZ/asm-18.ll +++ b/llvm/test/CodeGen/SystemZ/asm-18.ll @@ -290,11 +290,14 @@ define void @f12() { } ; Test selects involving high registers. +; Note that we prefer to use a LOCR and move the result to a high register. define void @f13(i32 %x, i32 %y) { ; CHECK-LABEL: f13: -; CHECK: llihl [[REG:%r[0-5]]], 0 -; CHECK: cije %r2, 0 -; CHECK: iihf [[REG]], 2102030405 +; CHECK-DAG: chi %r2, 0 +; CHECK-DAG: iilf [[REG1:%r[0-5]]], 2102030405 +; CHECK-DAG: lhi [[REG2:%r[0-5]]], 0 +; CHECK: locre [[REG1]], [[REG2]] +; CHECK: risbhg [[REG:%r[0-5]]], [[REG1]], 0, 159, 32 ; CHECK: blah [[REG]] ; CHECK: br %r14 %cmp = icmp eq i32 %x, 0 @@ -306,9 +309,10 @@ define void @f13(i32 %x, i32 %y) { ; Test selects involving low registers. define void @f14(i32 %x, i32 %y) { ; CHECK-LABEL: f14: -; CHECK: lhi [[REG:%r[0-5]]], 0 -; CHECK: cije %r2, 0 -; CHECK: iilf [[REG]], 2102030405 +; CHECK-DAG: chi %r2, 0 +; CHECK-DAG: iilf [[REG:%r[0-5]]], 2102030405 +; CHECK-DAG: lhi [[REG1:%r[0-5]]], 0 +; CHECK: locre [[REG]], [[REG1]] ; CHECK: blah [[REG]] ; CHECK: br %r14 %cmp = icmp eq i32 %x, 0 |
