[AArch64][SVE] Asm: Support for contiguous ST1 (scalar+scalar) store instructions.

Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D46121

llvm-svn: 331260

8 files changed, 171 insertions, 0 deletions

diff --git a/llvm/test/MC/AArch64/SVE/st1b-diagnostics.s b/llvm/test/MC/AArch64/SVE/st1b-diagnostics.s
index 89964cd245d..a4d879b7cc6 100644
--- a/llvm/test/MC/AArch64/SVE/st1b-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/st1b-diagnostics.s
@@ -83,3 +83,27 @@ st1b { v0.16b }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st1b { v0.16b }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+st1b z0.b, p0, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
+// CHECK-NEXT: st1b z0.b, p0, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1b z0.b, p0, [x0, x0, lsl #1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
+// CHECK-NEXT: st1b z0.b, p0, [x0, x0, lsl #1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1b z0.b, p0, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
+// CHECK-NEXT: st1b z0.b, p0, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1b z0.b, p0, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
+// CHECK-NEXT: st1b z0.b, p0, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/st1b.s b/llvm/test/MC/AArch64/SVE/st1b.s
index 3d22f673217..8bc72253c97 100644
--- a/llvm/test/MC/AArch64/SVE/st1b.s
+++ b/llvm/test/MC/AArch64/SVE/st1b.s
@@ -102,3 +102,27 @@ st1b    { z21.d }, p5, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x65,0xe4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 f5 65 e4 <unknown>
+
+st1b    { z0.b }, p0, [x0, x0]
+// CHECK-INST: st1b    { z0.b }, p0, [x0, x0]
+// CHECK-ENCODING: [0x00,0x40,0x00,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 00 e4 <unknown>
+
+st1b    { z0.h }, p0, [x0, x0]
+// CHECK-INST: st1b    { z0.h }, p0, [x0, x0]
+// CHECK-ENCODING: [0x00,0x40,0x20,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 20 e4 <unknown>
+
+st1b    { z0.s }, p0, [x0, x0]
+// CHECK-INST: st1b    { z0.s }, p0, [x0, x0]
+// CHECK-ENCODING: [0x00,0x40,0x40,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 40 e4 <unknown>
+
+st1b    { z0.d }, p0, [x0, x0]
+// CHECK-INST: st1b    { z0.d }, p0, [x0, x0]
+// CHECK-ENCODING: [0x00,0x40,0x60,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 60 e4 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/st1d-diagnostics.s b/llvm/test/MC/AArch64/SVE/st1d-diagnostics.s
index be4e8ee0558..9aac52a51a2 100644
--- a/llvm/test/MC/AArch64/SVE/st1d-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/st1d-diagnostics.s
@@ -39,3 +39,32 @@ st1d { v0.2d }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st1d { v0.2d }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+st1d z0.d, p0, [x0, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
+// CHECK-NEXT: st1d z0.d, p0, [x0, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1d z0.d, p0, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
+// CHECK-NEXT: st1d z0.d, p0, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1d z0.d, p0, [x0, x0, lsl #2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
+// CHECK-NEXT: st1d z0.d, p0, [x0, x0, lsl #2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1d z0.d, p0, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
+// CHECK-NEXT: st1d z0.d, p0, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1d z0.d, p0, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
+// CHECK-NEXT: st1d z0.d, p0, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/st1d.s b/llvm/test/MC/AArch64/SVE/st1d.s
index 0cc130e70c5..6c338613c82 100644
--- a/llvm/test/MC/AArch64/SVE/st1d.s
+++ b/llvm/test/MC/AArch64/SVE/st1d.s
@@ -30,3 +30,9 @@ st1d    { z21.d }, p5, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0xe5,0xe5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 f5 e5 e5 <unknown>
+
+st1d    { z0.d }, p0, [x0, x0, lsl #3]
+// CHECK-INST: st1d    { z0.d }, p0, [x0, x0, lsl #3]
+// CHECK-ENCODING: [0x00,0x40,0xe0,0xe5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 e0 e5 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/st1h-diagnostics.s b/llvm/test/MC/AArch64/SVE/st1h-diagnostics.s
index 63bdd57ce84..c72ae03b187 100644
--- a/llvm/test/MC/AArch64/SVE/st1h-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/st1h-diagnostics.s
@@ -68,3 +68,32 @@ st1h { v0.8h }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st1h { v0.8h }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+st1h z0.h, p0, [x0, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
+// CHECK-NEXT: st1h z0.h, p0, [x0, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1h z0.h, p0, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
+// CHECK-NEXT: st1h z0.h, p0, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1h z0.h, p0, [x0, x0, lsl #2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
+// CHECK-NEXT: st1h z0.h, p0, [x0, x0, lsl #2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1h z0.h, p0, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
+// CHECK-NEXT: st1h z0.h, p0, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1h z0.h, p0, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
+// CHECK-NEXT: st1h z0.h, p0, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/st1h.s b/llvm/test/MC/AArch64/SVE/st1h.s
index 615a3e08da5..4367b9cfa6a 100644
--- a/llvm/test/MC/AArch64/SVE/st1h.s
+++ b/llvm/test/MC/AArch64/SVE/st1h.s
@@ -78,3 +78,21 @@ st1h    { z31.d }, p7, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xff,0xef,0xe4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff ff ef e4 <unknown>
+
+st1h    { z0.h }, p0, [x0, x0, lsl #1]
+// CHECK-INST: st1h    { z0.h }, p0, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x00,0x40,0xa0,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 a0 e4 <unknown>
+
+st1h    { z0.s }, p0, [x0, x0, lsl #1]
+// CHECK-INST: st1h    { z0.s }, p0, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x00,0x40,0xc0,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 c0 e4 <unknown>
+
+st1h    { z0.d }, p0, [x0, x0, lsl #1]
+// CHECK-INST: st1h    { z0.d }, p0, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x00,0x40,0xe0,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 e0 e4 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/st1w-diagnostics.s b/llvm/test/MC/AArch64/SVE/st1w-diagnostics.s
index a224849144f..f479d602f7d 100644
--- a/llvm/test/MC/AArch64/SVE/st1w-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/st1w-diagnostics.s
@@ -56,3 +56,32 @@ st1w { v0.4s }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st1w { v0.4s }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+st1w z0.s, p0, [x0, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
+// CHECK-NEXT: st1w z0.s, p0, [x0, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1w z0.s, p0, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
+// CHECK-NEXT: st1w z0.s, p0, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1w z0.s, p0, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
+// CHECK-NEXT: st1w z0.s, p0, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1w z0.s, p0, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
+// CHECK-NEXT: st1w z0.s, p0, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1w z0.s, p0, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
+// CHECK-NEXT: st1w z0.s, p0, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/st1w.s b/llvm/test/MC/AArch64/SVE/st1w.s
index b64ebcf2963..892350b338e 100644
--- a/llvm/test/MC/AArch64/SVE/st1w.s
+++ b/llvm/test/MC/AArch64/SVE/st1w.s
@@ -54,3 +54,15 @@ st1w    { z21.d }, p5, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x65,0xe5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 f5 65 e5 <unknown>
+
+st1w    { z0.s }, p0, [x0, x0, lsl #2]
+// CHECK-INST: st1w    { z0.s }, p0, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x00,0x40,0x40,0xe5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 40 e5 <unknown>
+
+st1w    { z0.d }, p0, [x0, x0, lsl #2]
+// CHECK-INST: st1w    { z0.d }, p0, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x00,0x40,0x60,0xe5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 60 e5 <unknown>