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* Fix layering by moving X86DisassemblerDecoderCommon to SupportDavid Blaikie2018-03-232-469/+1
| | | | | | | | | This is used from llvm tblgen and the X86Disassembler - the only common library (apart from TableGen, which probably doesn't make sense to have as a dependency from a release tool (rather than a use-while-building-llvm tool) of LLVM) llvm-svn: 328393
* Move TargetLoweringObjectFile from CodeGen to Target to fix layeringDavid Blaikie2018-03-2319-19/+19
| | | | | | | It's implemented in Target & include from other Target headers, so the header should be in Target. llvm-svn: 328392
* [X86] Fix Windows `i1 zeroext` conventions to use i8 instead of i32Reid Kleckner2018-03-232-5/+15
| | | | | | | Both GCC and MSVC only look at the low byte of a boolean when it is passed. llvm-svn: 328386
* [Hexagon] Make findLoopInstr member of HexagonInstrInfoKrzysztof Parzyszek2018-03-232-3/+11
| | | | llvm-svn: 328367
* [Hexagon] Correct update of instruction offet in HW loop fixupKrzysztof Parzyszek2018-03-231-3/+7
| | | | llvm-svn: 328366
* [Hexagon] Boost profit for word-mask immediates, reduce for othersKrzysztof Parzyszek2018-03-231-10/+34
| | | | | | This avoids unnecessary splitting due to uninteresting immediates. llvm-svn: 328364
* [Hexagon] Assume all extendable branches to be of size 8 in relaxationKrzysztof Parzyszek2018-03-231-1/+8
| | | | | | | | | | | | | | The branch relaxation pass collects sizes of all instructions at the beginning, before any changes have been made. It then performs one pass over all branches to see which ones need to be extended. It does not account for the case when a previously valid branch becomes out-of-range due to relaxing other branches. This approach fixes this problem by assuming from the beginning that all extendable branches have been extended. This may cause unneeded relaxation in some cases, but avoids iteration and recomputing instruction sizes. llvm-svn: 328360
* [Hexagon] Incorrectly removing dead flag and adding kill flagKrzysztof Parzyszek2018-03-231-3/+4
| | | | | | | | | | | | The HexagonExpandCondsets pass is incorrectly removing the dead flag on a definition that is really dead, and adding a kill flag to a use that is tied to a definition. This causes an assert later during the machine scheduler when querying the live interval information. Patch by Brendon Cahoon. llvm-svn: 328357
* [Hexagon] Silence unused variable warning in Release buildsBenjamin Kramer2018-03-231-2/+2
| | | | llvm-svn: 328356
* [Hexagon] Fold offset in base+immediate loads/storesKrzysztof Parzyszek2018-03-231-9/+183
| | | | | | | | Optimize Ry = add(Rx,#n); memw(Ry+#0) = Rz => memw(Rx,#n) = Rz. Patch by Jyotsna Verma. llvm-svn: 328355
* [X86] Add itinerary to RCPSS*_Int and similar instructions.Craig Topper2018-03-231-2/+2
| | | | llvm-svn: 328353
* [X86] Add itineraries to ADD.*_DB instructions to match their normal ↵Craig Topper2018-03-231-11/+20
| | | | | | counterparts. llvm-svn: 328352
* [AMDGPU] Remove use of OpenCL triple environment and replace with function ↵Tony Tye2018-03-231-8/+4
| | | | | | | | | | | attribute for AMDGPU - Remove use of the opencl and amdopencl environment member of the target triple for the AMDGPU target. - Use function attribute to communicate to the AMDGPU backend to add implicit arguments for OpenCL kernels for the AMDHSA OS. Differential Revision: https://reviews.llvm.org/D43736 llvm-svn: 328349
* [Hexagon] Always generate mux out of predicated transfers if possibleKrzysztof Parzyszek2018-03-231-2/+10
| | | | | | | | | | | | HexagonGenMux would collapse pairs of predicated transfers if it assumed that the predicated .new forms cannot be created. Turns out that generating mux is preferable in almost all cases. Introduce an option -hexagon-gen-mux-threshold that controls the minimum distance between the instruction defining the predicate and the later of the two transfers. If the distance is closer than the threshold, mux will not be generated. Set the threshold to 0 by default. llvm-svn: 328346
* [Hexagon] Avoid early if-conversion for one sided branchesKrzysztof Parzyszek2018-03-231-12/+19
| | | | | | Patch by Anand Kodnani. llvm-svn: 328344
* [X86][Btver2] Cleanup TEST instructions to use JFPA (+JFPX on ymms) function ↵Simon Pilgrim2018-03-231-6/+6
| | | | | | unit llvm-svn: 328343
* [ARM] Fix "Constant pool entry out of range!" in Thumb1 modeAna Pazos2018-03-231-0/+1
| | | | | | | | | | | | | | | | | | | This patch fixes PR36658, "Constant pool entry out of range!" in Thumb1 mode. In ARMConstantIslands::optimizeThumb2JumpTables() in Thumb1 mode, adjustBBOffsetsAfter() is not calculating postOffset correctly by properly accounting for the padding that is required for the constant pool that immediately follows the jump table branch instruction. Reviewers: t.p.northover, eli.friedman Reviewed By: t.p.northover Subscribers: chrib, tstellar, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D44709 llvm-svn: 328341
* [Hexagon] Two fixes in early if-conversionKrzysztof Parzyszek2018-03-231-9/+12
| | | | | | | | | - Fix checking for vector predicate registers. - Avoid speculating llvm.lifetime.end intrinsic. Patch by Harsha Jagasia and Brendon Cahoon. llvm-svn: 328339
* [X86][Btver2] Cleanup MOVMSK instructions to use JFPA function unitSimon Pilgrim2018-03-231-2/+4
| | | | | | Add missing non-VEX and (V)PMOVMSKB instructions to the pattern llvm-svn: 328338
* [Hexagon] Copy subregisters in HexagonStoreWidenKrzysztof Parzyszek2018-03-231-8/+10
| | | | | | | | | When converting an instruction to the wider version, copy any subregisters if the original operand has a subregister. Patch by Brendon Cahoon. llvm-svn: 328333
* [X86][Btver2] Vector permutes use a JFPU01 scheduler pipe and JFPX/JVALU ↵Simon Pilgrim2018-03-231-18/+18
| | | | | | function unit llvm-svn: 328331
* [X86][Btver2] Vector store instructions use a JFPU1 scheduler pipe and ↵Simon Pilgrim2018-03-231-2/+2
| | | | | | JSAGU/JSTC function units llvm-svn: 328328
* Re-commit: [MachineLICM] Add functions to MachineLICM to hoist invariant storesZaara Syeda2018-03-234-44/+33
| | | | | | | | | | | | | | | | This patch adds functions to allow MachineLICM to hoist invariant stores. Currently, MachineLICM does not hoist any store instructions, however when storing the same value to a constant spot on the stack, the store instruction should be considered invariant and be hoisted. The function isInvariantStore iterates each operand of the store instruction and checks that each register operand satisfies isCallerPreservedPhysReg. The store may be fed by a copy, which is hoisted by isCopyFeedingInvariantStore. This patch also adds the PowerPC changes needed to consider the stack register as caller preserved. Differential Revision: https://reviews.llvm.org/D40196 llvm-svn: 328326
* [X86][Btver2] Cleanup DPPS/DPPD instructions to use JFPA/JFPM function unitsSimon Pilgrim2018-03-231-12/+12
| | | | llvm-svn: 328324
* [AArch64] Don't reduce the width of loads if it prevents combining a shiftJohn Brawn2018-03-232-0/+30
| | | | | | | | | | | | | | | Loads and stores can only shift the offset register by the size of the value being loaded, but currently the DAGCombiner will reduce the width of the load if it's followed by a trunc making it impossible to later combine the shift. Solve this by implementing shouldReduceLoadWidth for the AArch64 backend and make it prevent the width reduction if this is what would happen, though do allow it if reducing the load width will let us eliminate a later sign or zero extend. Differential Revision: https://reviews.llvm.org/D44794 llvm-svn: 328321
* [X86][Btver2] Fix MicroOps counts for DPPS/YMM memory folded instructionsSimon Pilgrim2018-03-231-3/+3
| | | | | | This was due to a misunderstanding over what llvm calls a micro-op (retirement unit) is actually called a macro-op on the AMD/Jaguar target. Folded loads don't affect num macro ops. llvm-svn: 328320
* [X86][Btver2] Cleanup SSE42 PCMPISTR/PCMPESTR string instructions to ↵Simon Pilgrim2018-03-231-5/+5
| | | | | | | | correctly use JFPU1 scheduler pipe followed by JLAGU/JSAGU/JFPA/JVALU function units Fixes throughput to match Agner/Fam16h-SoG as well. llvm-svn: 328318
* [ARM] Support float literals under XOChristof Douma2018-03-233-12/+30
| | | | | | | | | | | | | When targeting execute-only and fp-armv8, float constants in a compare resulted in instruction selection failures. This is now fixed by using vmov.f32 where possible, otherwise the floating point constant is lowered into a integer constant that is moved into a floating point register. This patch also restores using fpcmp with immediate 0 under fp-armv8. Change-Id: Ie87229706f4ed879a0c0cf66631b6047ed6c6443 llvm-svn: 328313
* [X86][Znver1] Fix instregex entries that don't match any instructions (D44687)Simon Pilgrim2018-03-231-4/+3
| | | | | | Reviewed by @GGanesh and @craig.topper llvm-svn: 328309
* [X86][SandyBridge] Fix missing comma that was causing string concatenation ↵Simon Pilgrim2018-03-231-1/+1
| | | | | | | | of 2 instregex entries Found while updating D44687 llvm-svn: 328308
* [X86][Btver2] Vector move/load/store instructions use a JFPU01 scheduler ↵Simon Pilgrim2018-03-231-6/+6
| | | | | | pipe and JFPX/JVALU function unit as well as the AGUs llvm-svn: 328304
* [AArch64] Clean-up a few over-eager regexps in models.Florian Hahn2018-03-232-26/+26
| | | | | | | | | Patch by Simon Pilgrim <llvm-dev@redking.me.uk> That is a slightly modified version of the AArch64 changes from Simon's D44687 . llvm-svn: 328303
* [ARM] Error out on .arm assembler directives on windowsMartin Storsjo2018-03-231-0/+7
| | | | | | | | Windows on arm is thumb only. Differential Revision: https://reviews.llvm.org/D43005 llvm-svn: 328298
* [X86] Give VPCMPEQQ the same itinerary as its SSE counterpart.Craig Topper2018-03-231-2/+2
| | | | llvm-svn: 328296
* [X86] Correct the latencies of SNB integer vector multiplies based on ↵Craig Topper2018-03-231-9/+25
| | | | | | Agner's data. Add missing MMX multiplies. llvm-svn: 328295
* [X86] Match vpblendvb/vblendvps/vblendvpd itineraries to the SSE equivalent. ↵Craig Topper2018-03-231-28/+23
| | | | | | Change pblendvb/blendvps/blendvpd to use WriteFVarBlend llvm-svn: 328294
* [X86] Change VPSADBW itinerary to SSE_INTALU_ITINS_P to match the SSE version.Craig Topper2018-03-231-2/+2
| | | | llvm-svn: 328293
* [X86] Give VLDDQUrm and LDDQUrm the same itinerary.Craig Topper2018-03-231-3/+4
| | | | llvm-svn: 328292
* [X86] Merge VMOVMSKBrr and MOVMSKBrr in the SNB sheduler model.Craig Topper2018-03-231-3/+2
| | | | | | The VMOVMSKBrr was in a separate InstRW with a lower latency, but I assume they should be the same and the higher latency matches Agners table so I'm going with that. llvm-svn: 328291
* [X86] Add VEXTRB/W/D/Q to Zen scheduler model.Craig Topper2018-03-231-2/+2
| | | | | | The SSE versions were present, but not the VEX version. llvm-svn: 328290
* [X86] Fix the itinerary for vextractps to match extractps.Craig Topper2018-03-231-2/+2
| | | | llvm-svn: 328289
* State that CFG is preserved in 'Falkor HW Prefetch Fix Late Phase'.Michael Zolotukhin2018-03-221-0/+1
| | | | | | That removes some redundant recomputations from the passes pipeline. llvm-svn: 328272
* [X86] Correct the VROUND regular expressions in Znver1 scheduler model to ↵Craig Topper2018-03-221-2/+2
| | | | | | account for r328254 llvm-svn: 328260
* [X86] Rename VROUNDYPS* and VROUNDYPD* instructions to VROUNDPSY* and ↵Craig Topper2018-03-228-81/+82
| | | | | | | | | | VROUNDPDY*. Fix itinerary mistake on all memory forms of VROUNDPD This makes the Y position consistent with other instructions. This should have been NFC, but while refactoring the multiclass I noticed that VROUNDPD memory forms were using the register itinerary. llvm-svn: 328254
* [X86][SkylakeClient] Fix a bunch of instructions that were incorrectly ↵Craig Topper2018-03-221-111/+93
| | | | | | | | assigned Port015 instead of Port01. The VEC ADD and VEC MUL units aren't present on port 5 on SkylakeClient. llvm-svn: 328241
* [CodeGen] Add a new pass for PostRA sinkJun Bum Lim2018-03-221-36/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This pass sinks COPY instructions into a successor block, if the COPY is not used in the current block and the COPY is live-in to a single successor (i.e., doesn't require the COPY to be duplicated). This avoids executing the the copy on paths where their results aren't needed. This also exposes additional opportunites for dead copy elimination and shrink wrapping. These copies were either not handled by or are inserted after the MachineSink pass. As an example of the former case, the MachineSink pass cannot sink COPY instructions with allocatable source registers; for AArch64 these type of copy instructions are frequently used to move function parameters (PhyReg) into virtual registers in the entry block.. For the machine IR below, this pass will sink %w19 in the entry into its successor (%bb.1) because %w19 is only live-in in %bb.1. ``` %bb.0: %wzr = SUBSWri %w1, 1 %w19 = COPY %w0 Bcc 11, %bb.2 %bb.1: Live Ins: %w19 BL @fun %w0 = ADDWrr %w0, %w19 RET %w0 %bb.2: %w0 = COPY %wzr RET %w0 ``` As we sink %w19 (CSR in AArch64) into %bb.1, the shrink-wrapping pass will be able to see %bb.0 as a candidate. With this change I observed 12% more shrink-wrapping candidate and 13% more dead copies deleted in spec2000/2006/2017 on AArch64. Reviewers: qcolombet, MatzeB, thegameg, mcrosier, gberry, hfinkel, john.brawn, twoh, RKSimon, sebpop, kparzysz Reviewed By: sebpop Subscribers: evandro, sebpop, sfertile, aemerson, mgorny, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D41463 llvm-svn: 328237
* [DAG, X86] Fix ISel-time node insertion idsNirav Dave2018-03-222-9/+15
| | | | | | | | | | | | | | | | As in SystemZ backend, correctly propagate node ids when inserting new unselected nodes into the DAG during instruction Seleciton for X86 target. Fixes PR36865. Reviewers: jyknight, craig.topper Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D44797 llvm-svn: 328233
* [X86] Correct the scheduling data for some of the 32 and 64 bit multiplies ↵Craig Topper2018-03-225-60/+27
| | | | | | to as best as I understand how they are implemented. llvm-svn: 328231
* [X86][Btver2] Conversion, MaskedLoad/MaskedStore and NTStores all are ↵Simon Pilgrim2018-03-221-20/+22
| | | | | | scheduled through the JFPU1 pipe llvm-svn: 328226
* [X86][Btver2] FCMP (inc FMAX/FMIN) instructions use the JFPA functional pipeSimon Pilgrim2018-03-221-6/+6
| | | | | | The ymm instructions are double pumped as well. llvm-svn: 328222
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