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| author | Craig Topper <craig.topper@intel.com> | 2018-03-23 06:41:38 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-03-23 06:41:38 +0000 |
| commit | 7f142b8bf1b73495bd53687a7ae2698e1106e3e3 (patch) | |
| tree | 1e694b1b614f4439c5a9f69c73b408eb0912a74b /llvm/lib/Target | |
| parent | fae4173b475a16aa12076fb752a7a905a560a2f3 (diff) | |
| download | bcm5719-llvm-7f142b8bf1b73495bd53687a7ae2698e1106e3e3.tar.gz bcm5719-llvm-7f142b8bf1b73495bd53687a7ae2698e1106e3e3.zip | |
[X86] Merge VMOVMSKBrr and MOVMSKBrr in the SNB sheduler model.
The VMOVMSKBrr was in a separate InstRW with a lower latency, but I assume they should be the same and the higher latency matches Agners table so I'm going with that.
llvm-svn: 328291
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedSandyBridge.td | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td index 155aa743d69..89d3a5f537b 100644 --- a/llvm/lib/Target/X86/X86SchedSandyBridge.td +++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td @@ -258,8 +258,7 @@ def SBWriteResGroup0 : SchedWriteRes<[SBPort0]> { let NumMicroOps = 1; let ResourceCycles = [1]; } -def: InstRW<[SBWriteResGroup0], (instregex "VPMOVMSKBrr", - "(V?)CVTSS2SDrr", +def: InstRW<[SBWriteResGroup0], (instregex "(V?)CVTSS2SDrr", "(V?)PSLLDri", "(V?)PSLLQri", "(V?)PSLLWri", @@ -551,7 +550,7 @@ def SBWriteResGroup7 : SchedWriteRes<[SBPort0]> { let NumMicroOps = 1; let ResourceCycles = [1]; } -def: InstRW<[SBWriteResGroup7], (instregex "PMOVMSKBrr", +def: InstRW<[SBWriteResGroup7], (instregex "(V?)PMOVMSKBrr", "VMOVMSKPDYrr", "(V?)MOVMSKPDrr", "VMOVMSKPSYrr", |
