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| author | Craig Topper <craig.topper@intel.com> | 2018-03-23 06:41:43 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-03-23 06:41:43 +0000 |
| commit | 4787b7f43422e75a75628b25766d92594555b433 (patch) | |
| tree | c527d50413f886a63fd6f98768c658db905c4549 /llvm/lib/Target | |
| parent | 659c66dfc1aab7902a61f17e21872f3180efc6d8 (diff) | |
| download | bcm5719-llvm-4787b7f43422e75a75628b25766d92594555b433.tar.gz bcm5719-llvm-4787b7f43422e75a75628b25766d92594555b433.zip | |
[X86] Correct the latencies of SNB integer vector multiplies based on Agner's data. Add missing MMX multiplies.
llvm-svn: 328295
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedSandyBridge.td | 34 |
1 files changed, 25 insertions, 9 deletions
diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td index 89d3a5f537b..0a04b188e0b 100644 --- a/llvm/lib/Target/X86/X86SchedSandyBridge.td +++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td @@ -676,13 +676,18 @@ def: InstRW<[SBWriteResGroup19], (instregex "ADC(8|16|32|64)ri", "SHRD(16|32|64)rri8")>; def SBWriteResGroup20 : SchedWriteRes<[SBPort0]> { - let Latency = 3; + let Latency = 5; let NumMicroOps = 1; let ResourceCycles = [1]; } def: InstRW<[SBWriteResGroup20], (instregex "MMX_PMADDUBSWrr", + "MMX_PMADDWDirr", "MMX_PMULHRSWrr", + "MMX_PMULHUWirr", + "MMX_PMULHWirr", + "MMX_PMULLWirr", "MMX_PMULUDQirr", + "MMX_PSADBWirr", "(V?)PMADDUBSWrr", "(V?)PMADDWDrr", "(V?)PMULDQrr", @@ -995,7 +1000,7 @@ def: InstRW<[SBWriteResGroup33], (instregex "MOV(8|16|32|64)mr", "(V?)MOVUPSmr")>; def SBWriteResGroup34 : SchedWriteRes<[SBPort0,SBPort15]> { - let Latency = 5; + let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,2]; } @@ -1475,9 +1480,7 @@ def SBWriteResGroup71 : SchedWriteRes<[SBPort0,SBPort23]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[SBWriteResGroup71], (instregex "MMX_PMADDUBSWrm", - "MMX_PMULHRSWrm", - "VTESTPDYrm", +def: InstRW<[SBWriteResGroup71], (instregex "VTESTPDYrm", "VTESTPSYrm")>; def SBWriteResGroup72 : SchedWriteRes<[SBPort1,SBPort23]> { @@ -1659,12 +1662,11 @@ def: InstRW<[SBWriteResGroup88], (instregex "SHLD(16|32|64)mri8", "SHRD(16|32|64)mri8")>; def SBWriteResGroup89 : SchedWriteRes<[SBPort0,SBPort23]> { - let Latency = 9; + let Latency = 11; let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[SBWriteResGroup89], (instregex "MMX_PMULUDQirm", - "(V?)PMADDUBSWrm", +def: InstRW<[SBWriteResGroup89], (instregex "(V?)PMADDUBSWrm", "(V?)PMADDWDrm", "(V?)PMULDQrm", "(V?)PMULHRSWrm", @@ -1675,6 +1677,20 @@ def: InstRW<[SBWriteResGroup89], (instregex "MMX_PMULUDQirm", "(V?)PMULUDQrm", "(V?)PSADBWrm")>; +def SBWriteResGroup89_2 : SchedWriteRes<[SBPort0,SBPort23]> { + let Latency = 10; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup89], (instregex "MMX_PMADDUBSWrm", + "MMX_PMADDWDirm" + "MMX_PMULHRSWrm", + "MMX_PMULHUWirm", + "MMX_PMULHWirm", + "MMX_PMULLWirm", + "MMX_PMULUDQirm", + "MMX_PSADBWirm")>; + def SBWriteResGroup90 : SchedWriteRes<[SBPort1,SBPort23]> { let Latency = 9; let NumMicroOps = 2; @@ -1932,7 +1948,7 @@ def: InstRW<[SBWriteResGroup107], (instregex "VCVTPD2DQYrm", "VCVTTPD2DQYrm")>; def SBWriteResGroup108 : SchedWriteRes<[SBPort0,SBPort23,SBPort15]> { - let Latency = 11; + let Latency = 13; let NumMicroOps = 4; let ResourceCycles = [1,1,2]; } |
