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| author | Craig Topper <craig.topper@intel.com> | 2018-03-22 22:17:11 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-03-22 22:17:11 +0000 |
| commit | adb173314dd65ef9f84e1d22ec1ac4f2582f3031 (patch) | |
| tree | 7729e38c4e7faea9867ebde9ce5712249631f8cd /llvm/lib/Target | |
| parent | 376294c23a047c19097a0603c3890ebdda86bff8 (diff) | |
| download | bcm5719-llvm-adb173314dd65ef9f84e1d22ec1ac4f2582f3031.tar.gz bcm5719-llvm-adb173314dd65ef9f84e1d22ec1ac4f2582f3031.zip | |
[X86] Correct the VROUND regular expressions in Znver1 scheduler model to account for r328254
llvm-svn: 328260
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleZnver1.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td index d2f3dacf38c..2ed0008757b 100644 --- a/llvm/lib/Target/X86/X86ScheduleZnver1.td +++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td @@ -1610,14 +1610,14 @@ def : InstRW<[ZnWriteVRCPPSLd], (instregex "VRCPPSYm")>; def ZnWriteROUNDr : SchedWriteRes<[ZnFPU3]> { let Latency = 4; } -def : InstRW<[ZnWriteROUNDr], (instregex "(V?)ROUND(Y?)(S|P)(S|D)r")>; +def : InstRW<[ZnWriteROUNDr], (instregex "(V?)ROUND(S|P)(S|D)(Y?)r")>; // v,m,i. def ZnWriteROUNDm : SchedWriteRes<[ZnAGU, ZnFPU3]> { let Latency = 11; let NumMicroOps = 2; } -def : InstRW<[ZnWriteROUNDm], (instregex "(V?)ROUND(Y?)(S|P)(S|D)m")>; +def : InstRW<[ZnWriteROUNDm], (instregex "(V?)ROUND(S|P)(S|D)(Y?)m")>; // DPPS. // x,x,i / v,v,v,i. |
