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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-03-23 12:08:23 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-03-23 12:08:23 +0000 |
| commit | 9ea14bbbb02b28b0e2d70fa04572e92a8cae7e23 (patch) | |
| tree | 0ee5d59a55a8d732ed6e758f089719ded8401268 /llvm/lib/Target | |
| parent | 2755893834efe0368c9846b18fdab2080eefe193 (diff) | |
| download | bcm5719-llvm-9ea14bbbb02b28b0e2d70fa04572e92a8cae7e23.tar.gz bcm5719-llvm-9ea14bbbb02b28b0e2d70fa04572e92a8cae7e23.zip | |
[X86][Znver1] Fix instregex entries that don't match any instructions (D44687)
Reviewed by @GGanesh and @craig.topper
llvm-svn: 328309
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleZnver1.td | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td index 7ddbb2762e5..2199b56d0e0 100644 --- a/llvm/lib/Target/X86/X86ScheduleZnver1.td +++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td @@ -367,8 +367,7 @@ def : InstRW<[WriteALULd], // INC DEC NOT NEG. // m. def : InstRW<[WriteALULd], - (instregex "(INC|DEC|NOT|NEG)(8|16|32|64)m", - "(INC|DEC)64(16|32)m")>; + (instregex "(INC|DEC|NOT|NEG)(8|16|32|64)m")>; // MUL IMUL. // r16. @@ -499,7 +498,7 @@ def ZnWriteRET : SchedWriteRes<[ZnALU03]> { let NumMicroOps = 2; } def : InstRW<[ZnWriteRET], (instregex "RET(L|Q|W)", "LRET(L|Q|W)", - "IRET(D|Q)", "RETF")>; + "IRET(16|32|64)")>; //-- Logic instructions --// @@ -913,7 +912,7 @@ def : InstRW<[ZnWriteFPU2], (instregex "MMX_MOVD64rr", "MMX_MOVD64to64rr", def : InstRW<[ZnWriteToALU2], (instregex "VMOVPQIto64rr")>; // (x)mm <- r64. -def : InstRW<[ZnWriteFPU2], (instregex "VMOV64toPQIrr", "VMOVZQI2PQIrr")>; +def : InstRW<[ZnWriteFPU2], (instregex "VMOV64toPQIrr")>; // (x)mm <- (x)mm. def : InstRW<[ZnWriteFPU], (instregex "MMX_MOVQ64rr")>; |
