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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-03-22 17:43:12 +0000 | 
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-03-22 17:43:12 +0000 | 
| commit | 0e031afa95470df1dfdf6428e4d4cfccd812bb4c (patch) | |
| tree | 3013a7828f995002debf58db182d3ced212efd83 /llvm/lib/Target | |
| parent | 71d36ad9f919d420beed28f6467123acb621f486 (diff) | |
| download | bcm5719-llvm-0e031afa95470df1dfdf6428e4d4cfccd812bb4c.tar.gz bcm5719-llvm-0e031afa95470df1dfdf6428e4d4cfccd812bb4c.zip | |
[X86][Btver2] FCMP (inc FMAX/FMIN) instructions use the JFPA functional pipe
The ymm instructions are double pumped as well.
llvm-svn: 328222
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleBtVer2.td | 12 | 
1 files changed, 6 insertions, 6 deletions
| diff --git a/llvm/lib/Target/X86/X86ScheduleBtVer2.td b/llvm/lib/Target/X86/X86ScheduleBtVer2.td index 462c2f02d54..21576e37121 100644 --- a/llvm/lib/Target/X86/X86ScheduleBtVer2.td +++ b/llvm/lib/Target/X86/X86ScheduleBtVer2.td @@ -625,13 +625,13 @@ def JWriteVMOVNTPYSt: SchedWriteRes<[JSTC, JSAGU]> {  }  def : InstRW<[JWriteVMOVNTPYSt], (instrs VMOVNTDQYmr, VMOVNTPDYmr, VMOVNTPSYmr)>; -def JWriteFCmp: SchedWriteRes<[JFPU0]> { +def JWriteFCmp: SchedWriteRes<[JFPU0, JFPA]> {    let Latency = 2;  }  def : InstRW<[JWriteFCmp], (instregex "(V)?M(AX|IN)(P|S)(D|S)rr",                                        "(V)?CMPP(S|D)rri", "(V)?CMPS(S|D)rr")>; -def JWriteFCmpLd: SchedWriteRes<[JLAGU, JFPU0]> { +def JWriteFCmpLd: SchedWriteRes<[JLAGU, JFPU0, JFPA]> {    let Latency = 7;  }  def : InstRW<[JWriteFCmpLd], (instregex "(V)?M(AX|IN)(P|S)(D|S)rm", @@ -712,15 +712,15 @@ def JWriteVBROADCASTYLd: SchedWriteRes<[JLAGU, JFPU01]> {  }  def : InstRW<[JWriteVBROADCASTYLd, ReadAfterLd], (instrs VBROADCASTSDYrm, VBROADCASTSSYrm)>; -def JWriteFPAY22: SchedWriteRes<[JFPU0]> { +def JWriteFPAY22: SchedWriteRes<[JFPU0, JFPA]> {    let Latency = 2; -  let ResourceCycles = [2]; +  let ResourceCycles = [1, 2];  }  def : InstRW<[JWriteFPAY22], (instregex "VCMPP(S|D)Yrri", "VM(AX|IN)P(D|S)Yrr")>; -def JWriteFPAY22Ld: SchedWriteRes<[JLAGU, JFPU0]> { +def JWriteFPAY22Ld: SchedWriteRes<[JLAGU, JFPU0, JFPA]> {    let Latency = 7; -  let ResourceCycles = [1, 2]; +  let ResourceCycles = [1, 1, 2];  }  def : InstRW<[JWriteFPAY22Ld, ReadAfterLd], (instregex "VCMPP(S|D)Yrmi", "VM(AX|IN)P(D|S)Yrm")>; | 

