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* [AArch64] Adjust the cost model for Exynos M1 and M2Evandro Menezes2017-11-171-43/+78
* [AMDGPU][MC][GFX9][disassembler] Corrected decoding of op_sel_hi for v_mad_mix*Dmitry Preobrazhensky2017-11-175-26/+26
* [ARM] Use dwarf exception handling on MinGWMartin Storsjo2017-11-172-3/+10
* AMDGPU: Replace list of SMEM buffer opcodesMatt Arsenault2017-11-172-10/+14
* AMDGPU: Fix breaking SMEM clausesMatt Arsenault2017-11-172-25/+45
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-17213-288/+288
* [ARM] 't' asm constraint should accept i32Yi Kong2017-11-161-1/+1
* [X86] Add DAG combine to remove sext i32->i64 from gather/scatter instructions.Craig Topper2017-11-161-1/+22
* [RISCV] Fix 64-bit data layout mismatch between backend and target descriptionMandeep Singh Grang2017-11-161-1/+1
* [X86] Pre-truncate gather/scatter indices that have element sizes larger than...Craig Topper2017-11-161-2/+19
* [X86] DAGCombinerInfo is in TargetLowering not X86TargetLowering.Craig Topper2017-11-161-1/+1
* [arc] Fix ambiguous overloaded operator errorDaniel Sanders2017-11-161-1/+1
* bpf: print backward branch target properlyYonghong Song2017-11-164-2/+18
* [arc] Update TargetInfo to include the new backend name argumentDaniel Sanders2017-11-161-1/+1
* Fix RISCV build after r318352Azharuddin Mohammed2017-11-161-2/+2
* [PPC] Change i32 constant in store instruction to i64Guozhi Wei2017-11-161-1/+16
* [TTI][X86] update costs of interleaved load\store of i64\doubleMohammed Agabaria2017-11-161-0/+6
* [X86] Update TTI to report that v1iX/v1fX types aren't legal for masked gathe...Craig Topper2017-11-161-2/+10
* Fix thinko in last commit.Eric Christopher2017-11-161-1/+1
* Add NDEBUG checks around LLVM_DUMP_METHOD functions for Wunused-function warn...Eric Christopher2017-11-162-2/+8
* [X86] Custom type legalize v2f32 masked gathers instead of trying to cleanup ...Craig Topper2017-11-161-26/+28
* bpf: enable llvm-objdump to print out symbolized jmp targetYonghong Song2017-11-161-0/+34
* [globalisel][tablegen] Generate rule coverage and use it to identify untested...Daniel Sanders2017-11-165-27/+34
* Try to fix WebAssembly build after r318352Reid Kleckner2017-11-161-2/+2
* Add backend name to Target to enable runtime info to be fed back into TableGenDaniel Sanders2017-11-1514-36/+39
* [AArch64] Adjust the cost model for Exynos M1 and M2Evandro Menezes2017-11-151-4/+14
* AMDGPU: Replace i64 add/sub loweringMatt Arsenault2017-11-155-9/+146
* [AArch64] Refactor the loads and stores optimizerEvandro Menezes2017-11-151-143/+143
* [X86] Add a return to the end of a switch to prevent an accidental fallthroug...Craig Topper2017-11-151-0/+1
* [PowerPC] Implement mayBeEmittedAsTailCall for PPCSean Fertile2017-11-152-0/+39
* [AArch64] Adjust the cost model for Exynos M1 and M2Evandro Menezes2017-11-151-17/+14
* [X86] Add CBW/CDQ/CDQE/CQO/CWD/CWDE to WriteALU schedule classSimon Pilgrim2017-11-152-32/+31
* [PowerPC] Split out the tailcall calling convention checks. NFC.Sean Fertile2017-11-151-11/+19
* [AArch64][SVE] Asm: Report SVE parsing diagnostics only onceSander de Smalen2017-11-151-25/+36
* [mips] Improve genConstMult() to work with arbitrary precisionPetar Jovanovic2017-11-151-11/+9
* [ARM] Split Arm jump table branch into i12 and rs suffixed versionsMomchil Velikov2017-11-155-210/+33
* [X86] Redefine the 128-bit version of VPGATHERQD and VGATHERQPS to use a VK2 ...Craig Topper2017-11-153-14/+24
* [PowerPC] fix up in redundant compare eliminationHiroshi Inoue2017-11-151-2/+6
* AMDGPU: Add separate definitions for DS insts without m0 useMatt Arsenault2017-11-151-154/+207
* AMDGPU: Don't use MUBUF vaddr if address may overflowMatt Arsenault2017-11-156-2/+60
* AMDGPU: Handle or in multi-use shl ptr combineMatt Arsenault2017-11-141-2/+2
* Reland "[mips][mt][6/7] Add support for mftr, mttr instructions."Simon Dardis2017-11-147-1/+375
* Fix unused variable warning.Richard Smith2017-11-141-1/+0
* AMDGPU: Error on stack size overflowMatt Arsenault2017-11-142-6/+12
* [SystemZ] Do not crash when selecting an OR of two constantsUlrich Weigand2017-11-141-2/+4
* [AArch64] Adjust the cost model for Exynos M1 and M2Evandro Menezes2017-11-141-11/+9
* [ARM, AArch64] Fix an assert message, Darwin isn't the only target supporting...Martin Storsjo2017-11-142-2/+4
* [SystemZ] Fix invalid codegen using RISBMux on out-of-range bitsUlrich Weigand2017-11-141-1/+9
* Mark intrinsics operating on the whole warp as IntrInaccessibleMemOnlyArtem Belevich2017-11-142-10/+21
* [X86] Fix typo in comment. NFCCraig Topper2017-11-141-2/+2
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