[X86] Add CBW/CDQ/CDQE/CQO/CWD/CWDE to WriteALU schedule class

Some CPUs are already overriding these sign extension instructions but we should be able to use the WriteALU schedule class by default.

Differential Revision: https://reviews.llvm.org/D39899

llvm-svn: 318308

2 files changed, 31 insertions, 32 deletions

diff --git a/llvm/lib/Target/X86/X86InstrExtension.td b/llvm/lib/Target/X86/X86InstrExtension.td
index af43d9f5332..bb391fd9c81 100644
--- a/llvm/lib/Target/X86/X86InstrExtension.td
+++ b/llvm/lib/Target/X86/X86InstrExtension.td
@@ -9,38 +9,36 @@
 //
 // This file describes the sign and zero extension operations.
 //
-//===----------------------------------------------------------------------===//
-
-let hasSideEffects = 0 in {
-  let Defs = [AX], Uses = [AL] in
-  def CBW : I<0x98, RawFrm, (outs), (ins),
-              "{cbtw|cbw}", [], IIC_CBW>, OpSize16;  // AX = signext(AL)
-  let Defs = [EAX], Uses = [AX] in
-  def CWDE : I<0x98, RawFrm, (outs), (ins),
-              "{cwtl|cwde}", [], IIC_CBW>, OpSize32; // EAX = signext(AX)
-
-  let Defs = [AX,DX], Uses = [AX] in
-  def CWD : I<0x99, RawFrm, (outs), (ins),
-              "{cwtd|cwd}", [], IIC_CBW>, OpSize16; // DX:AX = signext(AX)
-  let Defs = [EAX,EDX], Uses = [EAX] in
-  def CDQ : I<0x99, RawFrm, (outs), (ins),
-              "{cltd|cdq}", [], IIC_CBW>, OpSize32; // EDX:EAX = signext(EAX)
-
-
-  let Defs = [RAX], Uses = [EAX] in
-  def CDQE : RI<0x98, RawFrm, (outs), (ins),
-               "{cltq|cdqe}", [], IIC_CBW>;     // RAX = signext(EAX)
-
-  let Defs = [RAX,RDX], Uses = [RAX] in
-  def CQO  : RI<0x99, RawFrm, (outs), (ins),
-                "{cqto|cqo}", [], IIC_CBW>; // RDX:RAX = signext(RAX)
-}
-
-
-
-// Sign/Zero extenders
-let hasSideEffects = 0 in {
-def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
+//===----------------------------------------------------------------------===//

+

+let hasSideEffects = 0 in {

+  let Defs = [AX], Uses = [AL] in // AX = signext(AL)

+  def CBW : I<0x98, RawFrm, (outs), (ins),

+              "{cbtw|cbw}", [], IIC_CBW>, OpSize16, Sched<[WriteALU]>;

+  let Defs = [EAX], Uses = [AX] in // EAX = signext(AX)

+  def CWDE : I<0x98, RawFrm, (outs), (ins),

+              "{cwtl|cwde}", [], IIC_CBW>, OpSize32, Sched<[WriteALU]>;

+

+  let Defs = [AX,DX], Uses = [AX] in // DX:AX = signext(AX)

+  def CWD : I<0x99, RawFrm, (outs), (ins),

+              "{cwtd|cwd}", [], IIC_CBW>, OpSize16, Sched<[WriteALU]>;

+  let Defs = [EAX,EDX], Uses = [EAX] in // EDX:EAX = signext(EAX)

+  def CDQ : I<0x99, RawFrm, (outs), (ins),

+              "{cltd|cdq}", [], IIC_CBW>, OpSize32, Sched<[WriteALU]>;

+

+

+  let Defs = [RAX], Uses = [EAX] in // RAX = signext(EAX)

+  def CDQE : RI<0x98, RawFrm, (outs), (ins),

+               "{cltq|cdqe}", [], IIC_CBW>, Sched<[WriteALU]>;

+

+  let Defs = [RAX,RDX], Uses = [RAX] in // RDX:RAX = signext(RAX)

+  def CQO  : RI<0x99, RawFrm, (outs), (ins),

+                "{cqto|cqo}", [], IIC_CBW>, Sched<[WriteALU]>;

+}

+

+// Sign/Zero extenders

+let hasSideEffects = 0 in {

+def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),

                    "movs{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVSX_R16_R8>,
                    TB, OpSize16, Sched<[WriteALU]>;
 let mayLoad = 1 in
diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td
index 593e9b33aac..8f8ea9d8feb 100644
--- a/llvm/lib/Target/X86/X86SchedSandyBridge.td
+++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td
@@ -865,6 +865,7 @@ def SBWriteResGroup15 : SchedWriteRes<[SBPort0,SBPort015]> {
   let NumMicroOps = 2;
   let ResourceCycles = [1,1];
 }
+def: InstRW<[SBWriteResGroup15], (instregex "CWD")>;
 def: InstRW<[SBWriteResGroup15], (instregex "FNSTSW16r")>;
 
 def SBWriteResGroup16 : SchedWriteRes<[SBPort1,SBPort05]> {