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path: root/llvm/lib/Target/X86/X86InstrSystem.td
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* Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"Matt Arsenault2019-09-191-1/+1
* Revert r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"Hans Wennborg2019-09-191-1/+1
* GlobalISel: Don't materialize immarg arguments to intrinsicsMatt Arsenault2019-09-191-1/+1
* [X86] Remove CustomInserters for RDPKRU/WRPKRU. Use some custom lowering and ...Craig Topper2019-04-041-9/+4
* [X86] Remove X86 specific dag nodes for RDTSC/RDTSCP/RDPMC. NFCIAndrea Di Biagio2019-03-201-3/+3
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [cfi-verify] Support AArch64.Joel Galenson2018-07-131-1/+1
* [X86] Add NotMemoryFoldable to a bunch of instructions to suppress them from ...Craig Topper2018-06-121-22/+22
* [x86] invpcid LLVM intrinsicGabor Buella2018-05-251-3/+17
* [X86][CET] Changing -fcf-protection behavior to comply with gcc (LLVM part)Alexander Ivchenko2018-05-181-4/+5
* [X86] ptwrite intrinsicGabor Buella2018-05-101-7/+10
* [X86] Tag PCONFIG instruction with WriteSystem scheduler classSimon Pilgrim2018-05-081-0/+2
* [x86] Introduce the pconfig instructionGabor Buella2018-05-081-0/+17
* [X86] Remove 'opaque ptr' from the intel syntax parser and printer.Craig Topper2018-05-011-38/+38
* [X86] Use a MnemonicAlias instead of an InstAlias.Craig Topper2018-04-301-9/+0
* [X86] Make 64-bit sysret/sysexit not ambiguous in Intel assembly syntax.Craig Topper2018-04-291-2/+2
* [X86] Add suffixes to the LGDT/LIDT/SGDT/SIDT mnemonics in Intel syntax. Add ...Craig Topper2018-04-291-8/+17
* [X86] Remove SLDT64m instruction.Craig Topper2018-04-291-3/+0
* [X86] Remove OpSizeIgnore, it's not implemented any differently than OpSizeFi...Craig Topper2018-04-221-2/+2
* [X86] Introduce LLVM wbinvd intrinsicGabor Buella2018-04-121-1/+1
* [X86] Remove system/control schedule itineraries (PR37093)Simon Pilgrim2018-04-121-238/+189
* [X86] Describe wbnoinvd instructionGabor Buella2018-04-111-0/+6
* [x86] Model the direction flag (DF) separately from the rest of EFLAGS.Chandler Carruth2018-04-101-0/+13
* [X86] Change 32 and 64 bit versions of LSL instruction have a 16-bit memory o...Craig Topper2018-02-151-4/+6
* [X86] Tag CET-IBT instruction scheduler classesSimon Pilgrim2018-02-121-2/+2
* [X86] Add intrinsic support for the RDPID instructionCraig Topper2018-01-181-6/+14
* [X86] Disable sldtq parsing in 64-bit mode.Craig Topper2018-01-121-2/+2
* Instrument Control Flow For Indirect Branch TrackingOren Ben Simhon2018-01-091-0/+5
* [X86] Add 'Requires<[In64BitMode]>' to a bunch of instructions that only have...Craig Topper2017-12-151-30/+24
* [X86] Remove the 'Requires<[In64BitMode]>' from SHSTK instructions.Craig Topper2017-12-151-9/+5
* [X86] Fix XSAVE64 and similar instructions to not be allowed by the assembler...Craig Topper2017-12-151-22/+20
* [X86] Add RDMSR/WRMSR, RDPMC + RDTSC/RDTSCP schedule testsSimon Pilgrim2017-12-131-1/+2
* Strip trailing whitespace. NFCI.Simon Pilgrim2017-12-091-12/+12
* [X86] Tag FS/GS BASE R/W instruction scheduler classesSimon Pilgrim2017-12-091-9/+16
* [X86] Tag segment prefixes as NOP instruction scheduling classesSimon Pilgrim2017-12-091-7/+8
* [X86] Tag VIA PadLock crypto instructions scheduler classesSimon Pilgrim2017-12-081-1/+3
* [X86] Tag PKU/INVPCID/RDPID/SMAP/SMX/PTWRITE system instructions scheduler cl...Simon Pilgrim2017-12-081-16/+30
* Control-Flow Enforcement Technology - Shadow Stack support (LLVM side)Oren Ben Simhon2017-11-261-0/+58
* Avoid unecessary opsize byte in segment move to memoryNirav Dave2017-11-211-10/+2
* Revert r318678 to fix Clang testRichard Trieu2017-11-211-2/+10
* [X86] Avoid unecessary opsize byte in segment move to memoryNirav Dave2017-11-201-10/+2
* [X86] Change XRSTOR to use PS instead of TB to match XSAVE.Craig Topper2017-10-231-2/+2
* [X86] Add PTWRITE instruction for assembler and disassembler.Craig Topper2017-10-231-2/+14
* [X86] Add RDPID instruction for assembler and disassembler.Craig Topper2017-10-231-0/+9
* 'into' instruction should not be decoded as a valid instr in 64-bit modeAndrew V. Tischenko2017-09-201-1/+1
* [X86] Added missing mayLoad/mayStore attributes to some X86 instructions.Ayman Musa2017-04-131-5/+20
* [X86] Add xgetbv/xsetbv intrinsics to non-windows platformsGuy Blank2016-08-161-2/+5
* [X86] Don't model UD2/UD2B as a terminatorDavid Majnemer2016-08-091-1/+1
* test commit: remove trailing whitespaceZvi Rackover2016-06-181-1/+1
* [X86] Remove many operands that represent memory stores from outs to ins. The...Craig Topper2016-03-131-13/+13
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