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| author | Craig Topper <craig.topper@intel.com> | 2018-04-29 06:24:09 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-04-29 06:24:09 +0000 |
| commit | 18c4c8efafcbd7b15bdf70c1b67d2f22b4f5c034 (patch) | |
| tree | 1e6ca84d27fc7fb02d9045aaad0c1ba3cdc2bcc1 /llvm/lib/Target/X86/X86InstrSystem.td | |
| parent | d186829093e8c9b2d96cb5b10c81a6e78519e33b (diff) | |
| download | bcm5719-llvm-18c4c8efafcbd7b15bdf70c1b67d2f22b4f5c034.tar.gz bcm5719-llvm-18c4c8efafcbd7b15bdf70c1b67d2f22b4f5c034.zip | |
[X86] Add suffixes to the LGDT/LIDT/SGDT/SIDT mnemonics in Intel syntax. Add aliases based on 16/32-bit mode to choose the default.
This allows the instruction selection to follow mode in Intel syntax. And allows a suffix to be used to change size.
This matches gas behavior from what I could tell.
llvm-svn: 331138
Diffstat (limited to 'llvm/lib/Target/X86/X86InstrSystem.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSystem.td | 25 |
1 files changed, 17 insertions, 8 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSystem.td b/llvm/lib/Target/X86/X86InstrSystem.td index 190f2958876..514a30c7dcc 100644 --- a/llvm/lib/Target/X86/X86InstrSystem.td +++ b/llvm/lib/Target/X86/X86InstrSystem.td @@ -359,15 +359,15 @@ def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg), "verw\t$seg", []>, TB; let SchedRW = [WriteSystem] in { def SGDT16m : I<0x01, MRM0m, (outs), (ins opaque48mem:$dst), - "sgdt{w}\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>; + "sgdtw\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>; def SGDT32m : I<0x01, MRM0m, (outs), (ins opaque48mem:$dst), - "sgdt{l}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>; + "sgdt{l|d}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>; def SGDT64m : I<0x01, MRM0m, (outs), (ins opaque80mem:$dst), "sgdt{q}\t$dst", []>, TB, Requires <[In64BitMode]>; def SIDT16m : I<0x01, MRM1m, (outs), (ins opaque48mem:$dst), - "sidt{w}\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>; + "sidtw\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>; def SIDT32m : I<0x01, MRM1m, (outs), (ins opaque48mem:$dst), - "sidt{l}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>; + "sidt{l|d}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>; def SIDT64m : I<0x01, MRM1m, (outs), (ins opaque80mem:$dst), "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>; def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins), @@ -384,15 +384,15 @@ def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins), "sldt{q}\t$dst", []>, TB, Requires<[In64BitMode]>; def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src), - "lgdt{w}\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>; + "lgdtw\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>; def LGDT32m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src), - "lgdt{l}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>; + "lgdt{l|d}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>; def LGDT64m : I<0x01, MRM2m, (outs), (ins opaque80mem:$src), "lgdt{q}\t$src", []>, TB, Requires<[In64BitMode]>; def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src), - "lidt{w}\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>; + "lidtw\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>; def LIDT32m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src), - "lidt{l}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>; + "lidt{l|d}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>; def LIDT64m : I<0x01, MRM3m, (outs), (ins opaque80mem:$src), "lidt{q}\t$src", []>, TB, Requires<[In64BitMode]>; def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src), @@ -402,6 +402,15 @@ def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src), "lldt{w}\t$src", []>, TB; } // SchedRW +def : InstAlias<"sgdt\t$dst", (SGDT16m opaque48mem:$dst), 0>, Requires<[In16BitMode]>; +def : InstAlias<"sgdt\t$dst", (SGDT32m opaque48mem:$dst), 0>, Requires<[In32BitMode]>; +def : InstAlias<"sidt\t$dst", (SIDT16m opaque48mem:$dst), 0>, Requires<[In16BitMode]>; +def : InstAlias<"sidt\t$dst", (SIDT32m opaque48mem:$dst), 0>, Requires<[In32BitMode]>; +def : InstAlias<"lgdt\t$src", (LGDT16m opaque48mem:$src), 0>, Requires<[In16BitMode]>; +def : InstAlias<"lgdt\t$src", (LGDT32m opaque48mem:$src), 0>, Requires<[In32BitMode]>; +def : InstAlias<"lidt\t$src", (LIDT16m opaque48mem:$src), 0>, Requires<[In16BitMode]>; +def : InstAlias<"lidt\t$src", (LIDT32m opaque48mem:$src), 0>, Requires<[In32BitMode]>; + //===----------------------------------------------------------------------===// // Specialized register support let SchedRW = [WriteSystem] in { |
