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| author | Craig Topper <craig.topper@intel.com> | 2018-04-22 01:24:58 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-04-22 01:24:58 +0000 |
| commit | 2a28336f343210d002568e52892fd7abd4d82c3a (patch) | |
| tree | 37e894f4fe3f653bb5951fcd9d951ca765445f15 /llvm/lib/Target/X86/X86InstrSystem.td | |
| parent | e33ed7d667c8daf22b544c77c6bbb6e919d2f3f0 (diff) | |
| download | bcm5719-llvm-2a28336f343210d002568e52892fd7abd4d82c3a.tar.gz bcm5719-llvm-2a28336f343210d002568e52892fd7abd4d82c3a.zip | |
[X86] Remove OpSizeIgnore, it's not implemented any differently than OpSizeFixed.
llvm-svn: 330532
Diffstat (limited to 'llvm/lib/Target/X86/X86InstrSystem.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSystem.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSystem.td b/llvm/lib/Target/X86/X86InstrSystem.td index 8e8d5b67048..3e9c264a693 100644 --- a/llvm/lib/Target/X86/X86InstrSystem.td +++ b/llvm/lib/Target/X86/X86InstrSystem.td @@ -171,7 +171,7 @@ def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src), "mov{q}\t{$src, $dst|$dst, $src}", []>; let mayStore = 1 in { def MOV16ms : I<0x8C, MRMDestMem, (outs), (ins i16mem:$dst, SEGMENT_REG:$src), - "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSizeIgnore; + "mov{w}\t{$src, $dst|$dst, $src}", []>; } def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src), "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16; @@ -181,7 +181,7 @@ def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src), "mov{q}\t{$src, $dst|$dst, $src}", []>; let mayLoad = 1 in { def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src), - "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSizeIgnore; + "mov{w}\t{$src, $dst|$dst, $src}", []>; } } // SchedRW |
