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path: root/llvm/lib/Target/X86/X86InstrInfo.cpp
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* X86-FMA3: Implemented commute transformations FMA*_Int instructions.Vyacheslav Klochkov2015-11-131-118/+206
* My first/test commit. Removed a trailing whitespace.Vyacheslav Klochkov2015-11-121-1/+1
* Improved the operands commute transformation for X86-FMA3 instructions.Andrew Kaylor2015-11-061-27/+326
* Warning fix.Simon Pilgrim2015-11-041-2/+2
* [X86][SSE] Add general memory folding for (V)INSERTPS instructionSimon Pilgrim2015-11-041-7/+71
* Created new X86 FMA3 opcodes (FMA*_Int) that are used now for lowering of sca...Andrew Kaylor2015-11-041-0/+24
* AVX512: Add AVX-512 not materializable instructions. Igor Breger2015-10-261-1/+29
* [WinEH] Make FuncletLayout more robust against catchretDavid Majnemer2015-10-011-3/+5
* [x86] enable machine combiner reassociations for 256-bit vector logical integ...Sanjay Patel2015-09-301-0/+3
* Improved the interface of methods commuting operands, improved X86-FMA3 mem-f...Andrew Kaylor2015-09-281-59/+57
* [Machine Combiner] Refactor machine reassociation code to be target-independent.Chad Rosier2015-09-211-206/+9
* AVX-512: shufflevector for i1 vectors <2 x i1> .. <64 x i1>Elena Demikhovsky2015-09-171-0/+4
* [x86] enable machine combiner reassociations for 128-bit vector logical integ...Sanjay Patel2015-09-121-0/+6
* revert r247506; need to verify changes in existing testsSanjay Patel2015-09-121-6/+0
* [x86] enable machine combiner reassociations for 128-bit vector logical integ...Sanjay Patel2015-09-121-0/+6
* [x86] enable machine combiner reassociations for scalar 'xor' instsSanjay Patel2015-09-031-0/+4
* rename "slow-unaligned-mem-under-32" to slow-unaligned-mem-16" (NFCI)Sanjay Patel2015-09-011-3/+3
* [x86] enable machine combiner reassociations for scalar 'or' instsSanjay Patel2015-08-311-0/+4
* [MIR Serialization] static -> static const in getSerializable*MachineOperandT...Hal Finkel2015-08-301-1/+1
* [x86] enable machine combiner reassociations for scalar 'and' instsSanjay Patel2015-08-281-1/+5
* Expose hasLiveCondCodeDef as a member function of the X86InstrInfo class. NFCAndrew Kaylor2015-08-261-1/+1
* [x86] enable machine combiner reassociations for 256-bit vector min/maxSanjay Patel2015-08-211-0/+4
* [x86] invert logic for attribute 'FeatureFastUAMem'Sanjay Patel2015-08-211-3/+8
* [x86] enable machine combiner reassociations for 128-bit vector min/maxSanjay Patel2015-08-211-0/+8
* [x86] enable machine combiner reassociations for scalar double-precision min/maxSanjay Patel2015-08-191-0/+4
* [x86] enable machine combiner reassociations for scalar single-precision maxi...Sanjay Patel2015-08-191-0/+2
* [x86] enable machine combiner reassociations for scalar single-precision mini...Sanjay Patel2015-08-151-0/+6
* fix typo; NFCSanjay Patel2015-08-121-1/+1
* [x86] enable machine combiner reassociations for 256-bit vector FP mul/addSanjay Patel2015-08-121-0/+4
* PseudoSourceValue: Replace global manager with a manager in a machine function.Alex Lorenz2015-08-111-2/+2
* [x86] enable machine combiner reassociations for 128-bit vector single/double...Sanjay Patel2015-08-111-2/+6
* x86: Emit LAHF/SAHF instead of PUSHF/POPFJF Bastien2015-08-101-26/+51
* fix minsize detection: minsize attribute implies optimizing for sizeSanjay Patel2015-08-101-5/+2
* fix minsize detection: minsize attribute implies optimizing for sizeSanjay Patel2015-08-101-3/+1
* [x86] enable machine combiner reassociations for 128-bit vector single/double...Sanjay Patel2015-08-081-0/+4
* MIR Serialization: Initial serialization of the machine operand target flags.Alex Lorenz2015-08-061-0/+35
* Revert "Fix MO's analyzePhysReg, it was confusing sub- and super-registers. P...JF Bastien2015-08-051-48/+26
* Fix MO's analyzePhysReg, it was confusing sub- and super-registers. Problem p...JF Bastien2015-08-051-26/+48
* wrap OptSize and MinSize attributes for easier and consistent access (NFCI)Sanjay Patel2015-08-041-2/+3
* [x86] machine combiner reassociation: mark EFLAGS operand as 'dead'Sanjay Patel2015-08-041-4/+43
* [x86] reassociate integer multiplies using machine combiner passSanjay Patel2015-07-311-10/+30
* push fast-math check for machine-combiner reassociations into instruction-typ...Sanjay Patel2015-07-301-7/+4
* fix invalid load folding with SSE/AVX FP logical instructions (PR22371)Sanjay Patel2015-07-281-12/+3
* [X86] Allow load folding into PUSH instructionsMichael Kuperstein2015-07-231-4/+11
* Remove TargetInstrInfo::canFoldMemoryOperandSimon Pilgrim2015-07-191-56/+0
* [MMX] Use the appropriate instructions for GR64 <-> VR64 copies.Bruno Cardoso Lopes2015-07-141-2/+2
* [x86] enable machine combiner reassociations for scalar double-precision mult...Sanjay Patel2015-07-091-1/+3
* [x86] enable machine combiner reassociations for scalar double-precision addsSanjay Patel2015-07-091-0/+2
* [x86] enable machine combiner reassociations for scalar single-precision mult...Sanjay Patel2015-07-081-2/+4
* [X86][SSE] Added (V)ROUNDSD + (V)ROUNDSS stack folding supportSimon Pilgrim2015-07-081-4/+8
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