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| author | Sanjay Patel <spatel@rotateright.com> | 2015-09-12 19:47:50 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2015-09-12 19:47:50 +0000 |
| commit | 8b960d22ad4bc724b89e17f9ab0be9e6a468dd53 (patch) | |
| tree | ed34027d6e8f63d358df1f5d658092ffe8a505ce /llvm/lib/Target/X86/X86InstrInfo.cpp | |
| parent | 49b531a08d13fbb3a2099c7dbb38e212a9735478 (diff) | |
| download | bcm5719-llvm-8b960d22ad4bc724b89e17f9ab0be9e6a468dd53.tar.gz bcm5719-llvm-8b960d22ad4bc724b89e17f9ab0be9e6a468dd53.zip | |
[x86] enable machine combiner reassociations for 128-bit vector logical integer insts (2nd try)
The changes in:
test/CodeGen/X86/machine-cp.ll
are just due to scheduling differences after some logic instructions were reassociated.
llvm-svn: 247516
Diffstat (limited to 'llvm/lib/Target/X86/X86InstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 8b883162999..446d4bce155 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -6408,6 +6408,12 @@ static bool isAssociativeAndCommutative(const MachineInstr &Inst) { case X86::IMUL16rr: case X86::IMUL32rr: case X86::IMUL64rr: + case X86::PANDrr: + case X86::PORrr: + case X86::PXORrr: + case X86::VPANDrr: + case X86::VPORrr: + case X86::VPXORrr: // Normal min/max instructions are not commutative because of NaN and signed // zero semantics, but these are. Thus, there's no need to check for global // relaxed math; the instructions themselves have the properties we need. |
