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author | Sanjay Patel <spatel@rotateright.com> | 2015-07-08 22:35:20 +0000 |
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committer | Sanjay Patel <spatel@rotateright.com> | 2015-07-08 22:35:20 +0000 |
commit | 093fb170a6cf4391ed2314fc449e76ce49413e01 (patch) | |
tree | a72473e44e2e15716731ece7532346289d0b0794 /llvm/lib/Target/X86/X86InstrInfo.cpp | |
parent | ddaf6a7259a5f56431ca7889c912601e94d1ce20 (diff) | |
download | bcm5719-llvm-093fb170a6cf4391ed2314fc449e76ce49413e01.tar.gz bcm5719-llvm-093fb170a6cf4391ed2314fc449e76ce49413e01.zip |
[x86] enable machine combiner reassociations for scalar single-precision multiplies
llvm-svn: 241752
Diffstat (limited to 'llvm/lib/Target/X86/X86InstrInfo.cpp')
-rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index dd2d04dbe49..5484ae91855 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -6405,11 +6405,13 @@ static bool hasReassocSibling(const MachineInstr &Inst, bool &Commuted) { // TODO: There are many more machine instruction opcodes to match: // 1. Other data types (double, integer, vectors) -// 2. Other math / logic operations (mul, and, or) +// 2. Other math / logic operations (and, or) static bool isAssociativeAndCommutative(unsigned Opcode) { switch (Opcode) { - case X86::VADDSSrr: case X86::ADDSSrr: + case X86::VADDSSrr: + case X86::MULSSrr: + case X86::VMULSSrr: return true; default: return false; |