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path: root/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
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* When updating a tSpill/tRestore instruction to be a tSTRr/tLDRr, correctlyJim Grosbach2011-01-131-4/+7
* Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs a...Anton Korobeynikov2011-01-101-4/+4
* If we're not using reg+reg offset we're using reg+imm, set the opcodeEric Christopher2010-12-211-2/+2
* Add tSpill and tRestore to the opcodes to replace with tSTRi and tLDRiBill Wendling2010-12-161-0/+2
* Thumb1 had two patterns for the same load-from-constant-pool instruction.Jim Grosbach2010-12-151-1/+1
* If we're changing the frame register to a physical register other than SP, weBill Wendling2010-12-151-27/+37
* The tLDR et al instructions were emitting either a reg/reg or reg/immBill Wendling2010-12-141-7/+4
* Avoid release build warnings.Benjamin Kramer2010-11-191-2/+2
* Move hasFP() and few related hooks to TargetFrameInfo.Anton Korobeynikov2010-11-181-15/+5
* First step of huge frame-related refactoring: move emit{Prologue,Epilogue} ou...Anton Korobeynikov2010-11-151-203/+0
* Revert r114340 (improvements in Darwin function prologue/epilogue), as it brokeJim Grosbach2010-11-021-11/+27
* Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do anyJim Grosbach2010-10-191-8/+7
* Simplify ARM callee-saved register handling by removing the distinctionJim Grosbach2010-09-201-27/+11
* Re-apply r112883:Jim Grosbach2010-09-031-3/+13
* Revert "For ARM stack frames that utilize variable sized objects and have eit...Daniel Dunbar2010-09-031-13/+3
* For ARM stack frames that utilize variable sized objects and have eitherJim Grosbach2010-09-021-3/+13
* Simplify eliminateFrameIndex() interface back down now that PEI doesn't needJim Grosbach2010-08-261-13/+4
* Add Thumb1 support for virtual frame indices.Jim Grosbach2010-08-191-112/+137
* Re-apply r110655 with fixes. Epilogue must restore sp from fp if the function...Evan Cheng2010-08-101-6/+5
* Revert r110655, "Fix ARM hasFP() semantics. It should return true whenever FPDaniel Dunbar2010-08-101-5/+6
* Fix ARM hasFP() semantics. It should return true whenever FP register isEvan Cheng2010-08-101-6/+5
* Constify some arguments.Eric Christopher2010-07-201-1/+1
* Make getPhysicalRegisterRegClass non-virtual. Should be able to remove it soon.Rafael Espindola2010-07-111-15/+0
* skip dbg_value instructionsJim Grosbach2010-06-291-0/+2
* rdar://7937137 - dbg values not being handled in thumb1 version ofJim Grosbach2010-05-041-0/+7
* ReuseFrameIndexVals is used in multiple files, so it can't be static.Dan Gohman2010-04-151-1/+4
* Add const qualifiers to CodeGen's use of LLVM IR constructs.Dan Gohman2010-04-151-1/+1
* use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()Chris Lattner2010-04-021-3/+2
* Change ARM ld/st multiple instructions to have variant instructions forBob Wilson2010-03-131-3/+2
* comment why we use custom epilogue for t1 functions using vaargs.Jim Grosbach2010-03-101-0/+5
* Clear up the last (famous last words) frame index value reuse issues for Thumb1.Jim Grosbach2010-03-101-1/+1
* Change the Value argument to eliminateFrameIndex to a type-tagged value. ThisJim Grosbach2010-03-091-2/+3
* scavenged frame index value re-use gets confused when more than one baseJim Grosbach2010-03-091-0/+7
* Thumb1 epilogue code generation needs to take into account that callee-savedJim Grosbach2010-03-061-4/+18
* handle very large call frames when require SPAdj != 0 for Thumb1Jim Grosbach2010-02-241-3/+3
* Remove predicates when changing an add into an unpredicable mov.Jakob Stoklund Olesen2010-01-191-2/+6
* improve portability to avoid conflicting with std::next in c++'0x.Chris Lattner2009-12-031-1/+1
* Use Unified Assembly Syntax for the ARM backend.Jim Grosbach2009-11-091-1/+1
* 80-column cleanup of file header commentsJim Grosbach2009-11-071-2/+3
* Cleanup now that frame index scavenging via post-pass is working for ARM and ...Jim Grosbach2009-10-281-12/+0
* Trim more includes.Evan Cheng2009-10-221-1/+0
* Missing piece of the ARM frame index post-scavenging conditionalizationJim Grosbach2009-10-211-0/+12
* Now that all ARM subtargets use frame index scavenging, the Thumb1 requires*Jim Grosbach2009-10-201-12/+0
* Enable allocation of R3 in Thumb1Jim Grosbach2009-10-191-1/+0
* Adjust the scavenge register spilling to allow the target to choose anJim Grosbach2009-10-191-15/+32
* Cleanup up unused R3LiveIn tracking.Jim Grosbach2009-10-081-9/+0
* Re-enable register scavenging in Thumb1 by default.Jim Grosbach2009-10-081-64/+9
* reverting thumb1 scavenging default due to test failure while I figure out wh...Jim Grosbach2009-10-071-8/+64
* Enable thumb1 register scavenging by default.Jim Grosbach2009-10-071-64/+8
* Add register-reuse to frame-index register scavenging. When a target usesJim Grosbach2009-10-071-13/+19
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