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authorEric Christopher <echristo@apple.com>2010-12-21 02:12:07 +0000
committerEric Christopher <echristo@apple.com>2010-12-21 02:12:07 +0000
commit6df5ff8ce6bc412e65038661b08ae07f4d2afc09 (patch)
tree15fb5bd8e17cfdb383bbeb8c3c768e87d9de57c7 /llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
parent0b0c57806b0f4140f36bbebf2ca2cd87f523acca (diff)
downloadbcm5719-llvm-6df5ff8ce6bc412e65038661b08ae07f4d2afc09.tar.gz
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If we're not using reg+reg offset we're using reg+imm, set the opcode
to be the one we want to use. bugpoint reduced testcase is a little large, I'll see if I can simplify it down more. Fixes part of rdar://8782207 llvm-svn: 122307
Diffstat (limited to 'llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp')
-rw-r--r--llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp b/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
index 9f917234d13..07c12102798 100644
--- a/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
@@ -656,7 +656,7 @@ Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
*this, dl);
}
- MI.setDesc(TII.get(ARM::tLDRr));
+ MI.setDesc(TII.get(UseRR ? ARM::tLDRr : ARM::tLDRi));
MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
if (UseRR)
// Use [reg, reg] addrmode.
@@ -676,7 +676,7 @@ Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
} else
emitThumbRegPlusImmediate(MBB, II, VReg, FrameReg, Offset, TII,
*this, dl);
- MI.setDesc(TII.get(ARM::tSTRr));
+ MI.setDesc(TII.get(UseRR ? ARM::tSTRr : ARM::tSTRi));
MI.getOperand(i).ChangeToRegister(VReg, false, false, true);
if (UseRR) // Use [reg, reg] addrmode.
MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
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