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* [FPEnv][ARM] Add lowering of STRICT_FSETCC and STRICT_FSETCCSJohn Brawn2020-02-183-10/+75
* [FPEnv][AArch64] Add lowering and instruction selection for strict conversionsJohn Brawn2020-02-182-24/+54
* [FPEnv][AArch64] Add lowering and instruction selection for STRICT_FP_ROUNDJohn Brawn2020-02-182-8/+16
* Add lowering of STRICT_FSETCC and STRICT_FSETCCSJohn Brawn2020-02-183-11/+57
* Fix an unused variable warningHans Wennborg2020-02-121-1/+1
* [SystemZ] Bugfix in emitSelect()Jonas Paulsson2020-02-121-2/+3
* [AArch64] Add option to enable/disable load-store renaming.Florian Hahn2020-02-101-0/+7
* AMDGPU/EG,CM: Implement fsqrt using recip(rsqrt(x)) instead of x * rsqrt(x)Jan Vesely2020-02-103-4/+10
* [X86] Use MVT::i8 instead of MVT::i64 for shift amount in BuildSDIVPow2Craig Topper2020-02-101-1/+1
* [BPF] disable ReduceLoadWidth during SelectionDag phaseYonghong Song2020-02-101-0/+13
* Revert "[ARM] Improve codegen of volatile load/store of i64"Victor Campos2020-02-086-162/+6
* [X86] -fpatchable-function-entry=N,0: place patch label after ENDBR{32,64}Fangrui Song2020-02-051-0/+19
* [ARM][VecReduce] Force expand vector_reduce_fminDavid Green2020-02-051-3/+6
* [ARM] Expand vector reduction intrinsics on soft floatNikita Popov2020-02-051-1/+8
* [AArch64][ARM] Always expand ordered vector reductions (PR44600)Nikita Popov2020-02-052-2/+25
* AMDGPU: Fix handling of infinite loops in fragment shadersConnor Abbott2020-02-041-6/+73
* AMDGPU/R600: Emit rodata in text segmentJan Vesely2020-02-031-1/+1
* [BPF] fix a bug in BPFMISimplifyPatchable pass with -O0Yonghong Song2020-02-031-3/+4
* Revert "[AMDGPU] Invert the handling of skip insertion."Nicolai Hähnle2020-02-036-173/+6
* [RISCV] Scheduler description for the Rocket coreKai Wang2020-02-0311-186/+900
* [AArch64] -fpatchable-function-entry=N,0: place patch label after BTIFangrui Song2020-02-031-0/+20
* [WebAssembly] Fix resume-only case in Emscripten EHHeejin Ahn2020-01-291-1/+4
* [RISCV] Support ABI checking with per function target-featuresZakk Chen2020-01-273-10/+28
* Revert "[RISCV] Support ABI checking with per function target-features"Zakk Chen2020-01-273-27/+10
* [RISCV] Check the target-abi module flag matches the optionZakk Chen2020-01-273-12/+28
* [X86] Make `llc --help` output readable againRoman Lebedev2020-01-271-7/+7
* Add function attribute "patchable-function-prefix" to support -fpatchable-fun...Fangrui Song2020-01-242-6/+2
* [RISCV] Fix evaluating %pcrel_lo against global and weak symbolsJames Clarke2020-01-234-108/+79
* [AArch64] Don't rename registers with pseudo defs in Ld/St opt.Florian Hahn2020-01-221-0/+13
* [Transforms][RISCV] Remove a "using namespace llvm" from an include file. Fix...Craig Topper2020-01-171-2/+2
* Revert rG6078f2fedcac5797ac39ee5ef3fd7a35ef1202d5 - "[AArch64][GlobalISel]: S...Simon Pilgrim2020-01-151-38/+1
* [RISCV] Support ABI checking with per function target-featuresZakk Chen2020-01-153-10/+27
* Revert "[RISCV] Support ABI checking with per function target-features"Zakk Chen2020-01-153-27/+10
* Fix "pointer is null" static analyzer warning. NFCI.Simon Pilgrim2020-01-151-2/+1
* [AArch64][SVE] Fold variable into assert to silence unused variable warnings ...Benjamin Kramer2020-01-151-2/+2
* [AArch64][SVE] Add ptest intrinsicsCullen Rhodes2020-01-154-1/+54
* [RISCV] Support ABI checking with per function target-featuresZakk Chen2020-01-153-10/+27
* [AMDGPU] Invert the handling of skip insertion.cdevadas2020-01-156-6/+173
* [VE] Minimal codegen for empty functionsKazushi (Jam) Marukawa2020-01-1536-18/+2549
* [X86] Don't call LowerUINT_TO_FP_i32 for i32->f80 on 32-bit targets with sse2.Craig Topper2020-01-151-1/+1
* [PowerPC] Fix powerpcspe subtarget enablement in llvm backendJustin Hibbits2020-01-142-4/+3
* CMake: Make most target symbols hidden by defaultTom Stellard2020-01-14105-105/+114
* [BranchAlign] Add master --x86-branches-within-32B-boundaries flagPhilip Reames2020-01-141-2/+23
* [Win64] Handle FP arguments more gracefully under -mno-sseReid Kleckner2020-01-142-22/+31
* [X86] Drop an unneeded FIXME. NFCCraig Topper2020-01-141-1/+0
* [X86] Swap the 0 and the fudge factor in the constant pool for the 32-bit mod...Craig Topper2020-01-141-4/+4
* [codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU.Michael Liao2020-01-141-1/+1
* [AArch64][GlobalISel]: Support @llvm.{return,frame}address selection.Amara Emerson2020-01-141-1/+38
* [SVE] Add patterns for MUL immediate instruction.Danilo Carvalho Grael2020-01-142-2/+7
* [RISCV] Allow shrink wrapping for RISC-Vlewis-revill2020-01-141-4/+16
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