summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
Commit message (Expand)AuthorAgeFilesLines
* In preparation for moving ARM's TargetRegisterInfo to the TargetMachineEric Christopher2015-03-121-576/+0
* Remove the need to cache the subtarget in the ARM TargetRegisterInfoEric Christopher2015-03-121-11/+10
* Have TargetRegisterInfo::getLargestLegalSuperClass take aEric Christopher2015-03-101-4/+4
* Migrate ARM except for TTI, AsmPrinter, and frame loweringEric Christopher2015-01-291-16/+6
* [ARM] Remove dead assignment.Tilmann Scheller2014-12-191-1/+0
* [Thumb1] Re-write emitThumbRegPlusImmediateOliver Stannard2014-11-171-136/+134
* [ARM] Remove another redundant assignment.Tilmann Scheller2014-11-051-1/+0
* ARM: rework Thumb1 frame index rewritingTim Northover2014-10-201-102/+11
* [Thumb] Fix crash in Thumb1RegisterInfo::rewriteFrameIndexOliver Stannard2014-10-201-0/+1
* ARM: allow misaligned local variables in Thumb1 mode.Tim Northover2014-10-141-3/+1
* Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher2014-08-051-8/+4
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-7/+17
* Simplify resolveFrameIndex() signature.Jim Grosbach2014-04-021-4/+2
* Prune includes in ARM target.Craig Topper2014-03-221-2/+0
* [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer2014-03-021-1/+1
* ARM: remove unnecessary state-tracking during frame lowering.Tim Northover2013-11-041-5/+1
* Even more spelling fixes for "instruction".Robert Wilhelm2013-09-281-1/+1
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-3/+9
* Allow the register scavenger to spill multiple registersHal Finkel2013-03-221-1/+1
* Move the eliminateCallFramePseudoInstr method from TargetRegisterInfoEli Bendersky2013-02-211-41/+0
* [PEI] Pass the frame index operand number to the eliminateFrameIndex function.Chad Rosier2013-01-311-15/+12
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-4/+4
* Remove the explicit MachineInstrBuilder(MI) constructor.Jakob Stoklund Olesen2012-12-191-6/+3
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-6/+6
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-071-1/+2
* Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change s...Craig Topper2012-04-201-4/+4
* Reorder includes to match coding standards. Fix an issue or two exposed by that.Craig Topper2012-03-171-2/+1
* Handle regmasks in Thumb1RegisterInfo::saveScavengerRegister().Jakob Stoklund Olesen2012-03-011-0/+5
* Enable ARM base pointer when calling functions with large arguments.Jakob Stoklund Olesen2012-02-281-0/+16
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,...Jia Liu2012-02-181-1/+1
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-071-1/+1
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-4/+3
* Fix a regression from r138445. If we're loading from the frame/base pointerChad Rosier2011-10-101-0/+1
* Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.Jim Grosbach2011-08-241-14/+6
* 80 columns.Jim Grosbach2011-08-171-1/+2
* Tidy up.Jim Grosbach2011-08-171-2/+1
* Silence a bunch (but not all) "variable written but not read" warningsDuncan Sands2011-08-121-2/+2
* Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate A...Evan Cheng2011-07-201-1/+1
* Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions forEvan Cheng2011-07-181-1/+0
* Refact ARM Thumb1 tMOVr instruction family.Jim Grosbach2011-06-301-3/+3
* Thumb1 register to register MOV instruction is predicable.Jim Grosbach2011-06-301-11/+11
* Refactor away tSpill and tRestore pseudos in ARM backend.Jim Grosbach2011-06-291-5/+3
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-8/+8
* Use TRI::has{Sub,Super}ClassEq() where possible.Jakob Stoklund Olesen2011-06-021-1/+1
* Add a TRI::getLargestLegalSuperClass hook to provide an upper limit on regist...Jakob Stoklund Olesen2011-04-261-0/+8
* Trim a few unneeded includes.Jim Grosbach2011-04-181-2/+0
* Provide a legal pointer register class when targeting thumb1.Jakob Stoklund Olesen2011-03-311-0/+5
* In Thumb1 mode the constant might be materialized via the load from constpool...Anton Korobeynikov2011-03-051-3/+3
* Implement frame unwinding information emission for Thumb1. Not finished yet b...Anton Korobeynikov2011-03-051-25/+35
* Preliminary support for ARM frame save directives emission via MI flags.Anton Korobeynikov2011-03-051-13/+13
OpenPOWER on IntegriCloud