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* [ARM] Fill in FP16 FMA patternsDavid Green2020-01-051-0/+21
* Revert "[SCEV] Move ScalarEvolutionExpander.cpp to Transforms/Utils (NFC)."Florian Hahn2020-01-041-1/+1
* [SCEV] Move ScalarEvolutionExpander.cpp to Transforms/Utils (NFC).Florian Hahn2020-01-041-1/+1
* GlobalISel: Add type argument to getRegBankFromRegClassMatt Arsenault2020-01-032-4/+5
* Move tail call disabling code to target independent codeReid Kleckner2020-01-031-5/+2
* [ARM][NFC] Move tail predication checksSam Parker2020-01-031-69/+76
* [DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG fo...QingShan Zhang2020-01-031-0/+7
* DAG: Use TargetConstant for FENCE operandsMatt Arsenault2020-01-021-1/+1
* [ARM][Thumb][FIX] Add unwinding information to t4Diogo Sampaio2019-12-301-0/+2
* [ARM] Sink splat to ICmpDavid Green2019-12-302-2/+3
* [ARM][THUMB2] Allow emitting T3 types of add and subDiogo Sampaio2019-12-301-42/+33
* [SelectionDAG] Disallow indirect "i" constraintFangrui Song2019-12-291-4/+0
* [ARM] [Windows] Use COFF stubs for calls to extern_weak functionsMartin Storsjö2019-12-231-4/+6
* Revert "[ARM] Improve codegen of volatile load/store of i64"Victor Campos2019-12-206-158/+6
* [ARM][MVE] Fixes for tail predication.Sam Parker2019-12-203-12/+61
* [ARM][MVE] Tail predicate in the presence of vcmpSam Parker2019-12-203-76/+270
* [ARM][MVE] Tail predicate bottom/top muls.Sam Parker2019-12-201-0/+3
* [ARM] Improve codegen of volatile load/store of i64Victor Campos2019-12-196-6/+158
* [NFC][TTI] Add Alignment for isLegalMasked[Gather/Scatter]Anna Welker2019-12-181-0/+4
* [ARM] Move MVE opcode helper functions to ARMBaseInstrInfo. NFC.Sjoerd Meijer2019-12-163-108/+118
* [ARM] Fix in ICE when retrieving the number of micro-ops for vlldm/vlstmMomchil Velikov2019-12-131-2/+2
* [ARM][MVE] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=Off builds after...Fangrui Song2019-12-131-3/+4
* [ARM][MVE] Make VPT invalid for tail predicationSam Parker2019-12-131-3/+0
* [ARM][MVE] Add vector reduction intrinsics with two vector operandsMikhail Maltsev2019-12-132-40/+251
* [ARM][MVE] Add intrinsics for more immediate shifts.Simon Tatham2019-12-133-73/+182
* [ARM] Add custom strict fp conversion lowering when non-strict is customJohn Brawn2019-12-131-33/+64
* [NFC] Use EVT instead of bool for getSetCCInverse()Alex Richardson2019-12-131-5/+5
* Revert "[ARM][MVE] findVCMPToFoldIntoVPS. NFC."Sjoerd Meijer2019-12-131-28/+30
* [ARM][MVE][Intrinsics] Add *_x() variants of my *_m() intrinsics.Mark Murray2019-12-131-2/+2
* [ARM][MVE] findVCMPToFoldIntoVPS. NFC.Sjoerd Meijer2019-12-121-30/+28
* [ARM][MVE] Sink vector shift operandSam Parker2019-12-121-3/+28
* Revert "[ARM][MVE] Sink vector shift operand"Sam Parker2019-12-122-28/+3
* [ARM][MVE] Sink vector shift operandSam Parker2019-12-122-3/+28
* [IR] Split out target specific intrinsic enums into separate headersReid Kleckner2019-12-115-10/+15
* Rename TTI::getIntImmCost for instructions and intrinsicsReid Kleckner2019-12-112-2/+2
* [ARM][LowOverheadLoops] Remove dead loop update instructions.Sjoerd Meijer2019-12-111-2/+73
* [ARM][MVE] Add intrinsics for immediate shifts. (reland)Simon Tatham2019-12-111-20/+32
* [ARM][MVE] Refactor complex vector intrinsics [NFCI]Mikhail Maltsev2019-12-102-197/+116
* Revert "[ARM][MVE] Add intrinsics for immediate shifts."Eric Christopher2019-12-091-32/+20
* [ARM][MVE][Intrinsics] Add VQADDQ, VHADDQ, VRHADDQ, VQSUBQ, VHSUBQ, VQDMULHQ,...Mark Murray2019-12-091-68/+184
* [ARM][MVE][Intrinsics] Add VMULL[BT]Q_(INT|POLY) intrinsics.Mark Murray2019-12-092-38/+96
* [ARM] Fix NEON failure introduced by D71065.Simon Tatham2019-12-091-3/+5
* [ARM][MVE] Add intrinsics for immediate shifts.Simon Tatham2019-12-091-22/+32
* [ARM][MVE] Add complex vector intrinsicsMikhail Maltsev2019-12-091-0/+178
* [ARM] Enable MVE masked loads and storesDavid Green2019-12-091-1/+1
* [ARM] Teach the Arm cost model that a Shift can be folded into other instruct...David Green2019-12-092-6/+36
* [ARM] Additional tests and minor formatting. NFCDavid Green2019-12-091-43/+43
* [DebugInfo] Make describeLoadedValue() reg awareDavid Stenberg2019-12-092-6/+11
* Revert "[DebugInfo] Make describeLoadedValue() reg aware"David Stenberg2019-12-092-11/+6
* [DebugInfo] Make describeLoadedValue() reg awareDavid Stenberg2019-12-092-6/+11
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