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authorCraig Topper <craig.topper@gmail.com>2012-02-07 02:50:20 +0000
committerCraig Topper <craig.topper@gmail.com>2012-02-07 02:50:20 +0000
commite55c556a247a9c0decb4e256d9e897dfc9cf841d (patch)
tree9648cb86dd2f5fb9625baa9989eca6d9b53f8bfa /llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
parent0298834e46efc1db1a3f6aa156d028b6cbf63d5b (diff)
downloadbcm5719-llvm-e55c556a247a9c0decb4e256d9e897dfc9cf841d.tar.gz
bcm5719-llvm-e55c556a247a9c0decb4e256d9e897dfc9cf841d.zip
Convert assert(0) to llvm_unreachable
llvm-svn: 149961
Diffstat (limited to 'llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp')
-rw-r--r--llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp b/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
index e61c0a733b0..9c2f2c58575 100644
--- a/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
@@ -694,7 +694,7 @@ Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
// register. The offset is already handled in the vreg value.
MI.getOperand(i+1).ChangeToRegister(FrameReg, false, false, false);
} else {
- assert(false && "Unexpected opcode!");
+ llvm_unreachable("Unexpected opcode!");
}
// Add predicate back if it's needed.
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