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authorJim Grosbach <grosbach@apple.com>2011-08-17 19:53:53 +0000
committerJim Grosbach <grosbach@apple.com>2011-08-17 19:53:53 +0000
commit863752388662182e59f1647c4275359950ee182a (patch)
tree7eeda2b21c3d5b94f051549eb467ad26d9bd9b58 /llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
parent1cdd7fdf545a0f08b5ff69f340b30306b8b8d558 (diff)
downloadbcm5719-llvm-863752388662182e59f1647c4275359950ee182a.tar.gz
bcm5719-llvm-863752388662182e59f1647c4275359950ee182a.zip
Tidy up.
llvm-svn: 137856
Diffstat (limited to 'llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp')
-rw-r--r--llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp3
1 files changed, 1 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp b/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
index 107c86be70f..53476def9d4 100644
--- a/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
@@ -264,8 +264,7 @@ void llvm::emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
if (NeedPred)
MIB = AddDefaultPred(MIB);
MIB.setMIFlags(MIFlags);
- }
- else {
+ } else {
bool isKill = BaseReg != ARM::SP;
MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
if (NeedCC)
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