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| author | Oliver Stannard <oliver.stannard@arm.com> | 2018-02-08 14:31:22 +0000 |
|---|---|---|
| committer | Oliver Stannard <oliver.stannard@arm.com> | 2018-02-08 14:31:22 +0000 |
| commit | 133b6085e86f04491606f501c1e24efd611a792d (patch) | |
| tree | 9dfd21ee8585c864ad3830c0db439dcd636833c4 /llvm/lib/Target/ARM/Disassembler | |
| parent | 4039dbea77fda46c1a45b65a3e70b72e561e5752 (diff) | |
| download | bcm5719-llvm-133b6085e86f04491606f501c1e24efd611a792d.tar.gz bcm5719-llvm-133b6085e86f04491606f501c1e24efd611a792d.zip | |
[ARM] Re-commit r324600 with fixed LLVMBuild.txt
ARMDisassembler now depends on the banked register tables in ARMUtils, so the
LLVMBuild.txt needed updating to reflect this.
Original commit mesage:
[ARM] Fix disassembly of invalid banked register moves
When disassembling banked register move instructions, we don't have an
assembly syntax for the unallocated register numbers, so we have to
return Fail rather than SoftFail. Previously we were returning SoftFail,
then crashing in the InstPrinter as we have no way to represent these
encodings in an assembly string.
This also switches the decoder to use the table-generated list of banked
registers, removing the duplicated list of encodings.
Differential revision: https://reviews.llvm.org/D43066
llvm-svn: 324606
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler')
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 11 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/LLVMBuild.txt | 2 |
2 files changed, 3 insertions, 10 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 658a67511ff..f9a0a74bf8b 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -4205,15 +4205,8 @@ static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, // The table of encodings for these banked registers comes from B9.2.3 of the // ARM ARM. There are patterns, but nothing regular enough to make this logic // neater. So by fiat, these values are UNPREDICTABLE: - if (!R) { - if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 || - SysM == 0x1a || SysM == 0x1b) - return MCDisassembler::SoftFail; - } else { - if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 && - SysM != 0x16 && SysM != 0x1c && SysM != 0x1e) - return MCDisassembler::SoftFail; - } + if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) + return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(Val)); return MCDisassembler::Success; diff --git a/llvm/lib/Target/ARM/Disassembler/LLVMBuild.txt b/llvm/lib/Target/ARM/Disassembler/LLVMBuild.txt index a64a8a970c0..48eef05e4f2 100644 --- a/llvm/lib/Target/ARM/Disassembler/LLVMBuild.txt +++ b/llvm/lib/Target/ARM/Disassembler/LLVMBuild.txt @@ -19,5 +19,5 @@ type = Library name = ARMDisassembler parent = ARM -required_libraries = ARMDesc ARMInfo MCDisassembler Support +required_libraries = ARMDesc ARMInfo MCDisassembler Support ARMUtils add_to_library_groups = ARM |
