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| author | Simi Pallipurath <simi.pallipurath@arm.com> | 2018-03-06 15:21:19 +0000 |
|---|---|---|
| committer | Simi Pallipurath <simi.pallipurath@arm.com> | 2018-03-06 15:21:19 +0000 |
| commit | 75c6bfeac9480c6f2877522f064e71dd4c43a6e9 (patch) | |
| tree | 2b9744697d8e8b2d1c0b9b8e99b99bfd685798ff /llvm/lib/Target/ARM/Disassembler | |
| parent | a9daa969c13f7ffc55db6eb32ca928fb855c3394 (diff) | |
| download | bcm5719-llvm-75c6bfeac9480c6f2877522f064e71dd4c43a6e9.tar.gz bcm5719-llvm-75c6bfeac9480c6f2877522f064e71dd4c43a6e9.zip | |
[ARM]Decoding MSR with unpredictable destination register causes an assert
This patch handling:
Enable parsing of raw encodings of system registers .
Allows UNPREDICTABLE sysregs to be decoded to a raw number in the same way that disasslib does, rather than llvm crashing.
Disassemble msr/mrs with unpredictable sysregs as SoftFail.
Fix regression due to SoftFailing some encodings.
Patch by Chris Ryder
Differential revision:https://reviews.llvm.org/D43374
llvm-svn: 326803
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler')
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index f9a0a74bf8b..3ffa702462c 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -4149,7 +4149,6 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, case 0x8a: // msplim_ns case 0x8b: // psplim_ns case 0x91: // basepri_ns - case 0x92: // basepri_max_ns case 0x93: // faultmask_ns if (!(FeatureBits[ARM::HasV8MMainlineOps])) return MCDisassembler::Fail; @@ -4165,7 +4164,9 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, return MCDisassembler::Fail; break; default: - return MCDisassembler::Fail; + // Architecturally defined as unpredictable + S = MCDisassembler::SoftFail; + break; } if (Inst.getOpcode() == ARM::t2MSR_M) { |
