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path: root/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
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* Narrow right shifts need to encode their immediates differently from a normalBill Wendling2011-03-011-0/+25
| | | | | | | | | | shift. 16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0> 32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0> 64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0> llvm-svn: 126723
* Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 ↵Owen Anderson2011-02-081-13/+9
| | | | | | (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being. llvm-svn: 125127
* Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps.Jason W Kim2011-02-041-1/+37
| | | | | | | | | | | | | | | | (yes, this is different from R_ARM_CALL) - Adds a new method getARMBranchTargetOpValue() which handles the necessary distinction between the conditional and unconditional br/bl needed for ARM/ELF At least for ARM mode, the needed fixup for conditional versus unconditional br/bl is identical, but the ARM docs and existing ARM tools expect this reloc type... Added a few FIXME's for future naming fixups in ARMInstrInfo.td llvm-svn: 124895
* Add support for parsing and encoding ARM's official syntax for the BFI ↵Bruno Cardoso Lopes2011-01-181-0/+14
| | | | | | instruction llvm-svn: 123770
* Completed :lower16: / :upper16: support for movw / movt pairs on Darwin.Evan Cheng2011-01-141-22/+28
| | | | | | | | - Fixed :upper16: fix up routine. It should be shifting down the top 16 bits first. - Added support for Thumb2 :lower16: and :upper16: fix up. - Added :upper16: and :lower16: relocation support to mach-o object writer. llvm-svn: 123424
* Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a stepEvan Cheng2011-01-131-35/+27
| | | | | | | | in the right direction. It eliminated some hacks and will unblock codegen work. But it's far from being done. It doesn't reject illegal expressions, e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all. llvm-svn: 123369
* Mostly undo r123297, but move the default case in EvaluateAsPCRel to the topMatt Beaumont-Gay2011-01-121-3/+3
| | | | | | of the switch block to appease GCC. llvm-svn: 123317
* Prefer llvm_unreachable to assert(0)Matt Beaumont-Gay2011-01-121-3/+3
| | | | llvm-svn: 123297
* 1. Support ELF pcrel relocations for movw/movt:Jason W Kim2011-01-121-2/+37
| | | | | | | | R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC. 2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum. 3. Add support for 3 new elf section types (no-ops) llvm-svn: 123294
* MC: Move target specific fixup info descriptors to TargetAsmBackend instead ofDaniel Dunbar2010-12-161-39/+0
| | | | | | | the MCCodeEmitter, which seems like a better organization. - Also, cleaned up some magic constants while in the area. llvm-svn: 121953
* Delete an extra "Imm5 = ", caught by GCC's -Wsequence-point but not by ClangMatt Beaumont-Gay2010-12-161-1/+1
| | | | | | (see PR4579). llvm-svn: 121939
* Remove fixup_arm_thumb_ldst. The code was never calling the "fixup" stuff forBill Wendling2010-12-161-11/+1
| | | | | | it. I.e., it was always an immediate value. llvm-svn: 121932
* If we're changing the frame register to a physical register other than SP, weBill Wendling2010-12-151-2/+1
| | | | | | need to use tLDRi and tSTRi instead of tLDRspi and tSTRspi respectively. llvm-svn: 121915
* Implement cleanups suggested by Daniel.Owen Anderson2010-12-151-4/+4
| | | | llvm-svn: 121875
* Add fixups for Thumb LDR/STR instructions.Bill Wendling2010-12-151-3/+13
| | | | llvm-svn: 121858
* thumb adr fixup needs alignment just like the t2 version.Jim Grosbach2010-12-141-1/+2
| | | | llvm-svn: 121812
* Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755Jim Grosbach2010-12-141-0/+13
| | | | llvm-svn: 121798
* MC/ARM: Fix-up fixup offset for fixup_arm_branch target specific fixup.Daniel Dunbar2010-12-141-1/+1
| | | | llvm-svn: 121772
* The tLDR et al instructions were emitting either a reg/reg or reg/immBill Wendling2010-12-141-23/+17
| | | | | | | | | | | | | | | | instruction based on the t_addrmode_s# mode and what it returned. There is some obvious badness to this. In particular, it's hard to do MC-encoding when the instruction may change out from underneath you after the t_addrmode_s# variable is finally resolved. The solution is to revert a long-ago change that merged the reg/reg and reg/imm versions. There is the addition of several new addressing modes. They no longer have extraneous operands associated with them. I.e., if it's reg/reg we don't have to have a dummy zero immediate tacked on to the SDNode. There are some obvious cleanups here, which will happen shortly. llvm-svn: 121747
* Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering ↵Owen Anderson2010-12-141-0/+15
| | | | | | | | much later, which makes the entire process cleaner. llvm-svn: 121735
* Revert r121721, which broke buildbots.Owen Anderson2010-12-131-15/+0
| | | | llvm-svn: 121726
* Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. ↵Owen Anderson2010-12-131-0/+15
| | | | | | | | Provide correct fixups for Thumb2 ADR, which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup. llvm-svn: 121721
* In Thumb2, direct branches can be encoded as either a "short" conditional ↵Owen Anderson2010-12-131-2/+33
| | | | | | | | | | branch with a null predicate, or as a "long" direct branch. While the mnemonics are the same, they encode the branch offset differently, and the Darwin assembler appears to prefer the "long" form for direct branches. Thus, in the name of bitwise equivalence, provide encoding and fixup support for it. llvm-svn: 121710
* Add FIXMEJim Grosbach2010-12-101-0/+2
| | | | llvm-svn: 121598
* Attempt to get Thumb2 branch fixups working properly.Owen Anderson2010-12-101-2/+1
| | | | llvm-svn: 121593
* Fix merge error in my last fix to Thumb2 vldr fixups.Owen Anderson2010-12-101-1/+1
| | | | llvm-svn: 121588
* Fixups for Thumb2 vldr's need to have the effective PC aligned as well.Owen Anderson2010-12-101-1/+2
| | | | llvm-svn: 121587
* The MCFixupKindInfo table needs to be in the order that the enums wereBill Wendling2010-12-101-16/+19
| | | | | | declared. Add a note specifying this and spruce up the list a bit. llvm-svn: 121586
* Fix encoding of Thumb1 LDRB and STRB.Owen Anderson2010-12-101-0/+15
| | | | llvm-svn: 121581
* Trailing whitespace.Jim Grosbach2010-12-101-16/+16
| | | | llvm-svn: 121580
* Fix encoding of 'U' bit for Thumb2 STRD/LDRD instructions. rdar://8755726Jim Grosbach2010-12-101-4/+4
| | | | llvm-svn: 121524
* Thumb unconditional branch binary encoding. rdar://8754994Jim Grosbach2010-12-101-1/+13
| | | | llvm-svn: 121496
* Thumb conditional branch binary encodings. rdar://8745367Jim Grosbach2010-12-101-0/+12
| | | | llvm-svn: 121493
* Thumb ldr reg+imm offsets were encoded incorrectly. The scaling factor of theBill Wendling2010-12-091-36/+8
| | | | | | | t_addrmode_s# address modes is used for ASM printing, not for encoding. <rdar://problem/8745375> llvm-svn: 121417
* Use the new IsAligned fixup flag to improve fixup encodings for Thumb2 ↵Owen Anderson2010-12-091-1/+2
| | | | | | | | branches. This is still not perfect, but it gets many more of them correct than it did previously. llvm-svn: 121414
* Fix an issue in some Thumb fixups, where the effective PC address needs to ↵Owen Anderson2010-12-091-1/+2
| | | | | | | | | | be 4-byte aligned when calculating the offset. Add a new fixup flag to represent this, and use it for the one fixups that I have a testcase for needing this. It's quite likely that the other Thumb fixups will need this too, and to have their fixup encoding logic adjusted accordingly. llvm-svn: 121408
* Rename CB/CBZ specific fixup accordingly.Jim Grosbach2010-12-091-2/+2
| | | | llvm-svn: 121404
* Rename the encoder method for t_cbtarget to match.Jim Grosbach2010-12-091-4/+4
| | | | llvm-svn: 121399
* Fix Thumb2 fixups for ldr.Owen Anderson2010-12-091-1/+7
| | | | llvm-svn: 121350
* The BLX instruction is encoded differently than the BL, because why not? InBill Wendling2010-12-091-12/+16
| | | | | | | | | | particular, the immediate has 20-bits of value instead of 21. And bit 0 is '0' always. Going through the BL fixup encoding was trashing the "bit 0 is '0'" invariant. Attempt to get the encoding at slightly more correct with this. llvm-svn: 121336
* Fix Thumb2 BCC encoding and fixups.Owen Anderson2010-12-091-0/+4
| | | | llvm-svn: 121329
* Support the "target" encodings for the CB[N]Z instructions.Bill Wendling2010-12-081-28/+33
| | | | llvm-svn: 121308
* Add support for loading from a constant pool.Bill Wendling2010-12-081-3/+27
| | | | llvm-svn: 121226
* VLDR fixups need special handling under Thumb. While the encoding is the same,Owen Anderson2010-12-081-1/+7
| | | | | | the order of the bytes in the data stream is flipped around. llvm-svn: 121215
* Fix a warning about a variable which is only used in an assertion.Matt Beaumont-Gay2010-12-071-2/+2
| | | | llvm-svn: 121206
* Binary encoding for ARM tLDRspi and tSTRspi.Jim Grosbach2010-12-071-0/+19
| | | | llvm-svn: 121186
* Second attempt at converting Thumb2's LDRpci, including updating the ↵Owen Anderson2010-12-071-3/+8
| | | | | | gazillion places that need to know about it. llvm-svn: 121082
* Add fixup for Thumb1 BL/BLX instructions.Jim Grosbach2010-12-061-0/+24
| | | | llvm-svn: 121072
* Encode the 32-bit wide Thumb (and Thumb2) instructions with the high orderJim Grosbach2010-12-031-1/+9
| | | | | | halfword being emitted to the stream first. rdar://8728174 llvm-svn: 120848
* The tLDR instruction wasn't encoded properly:Bill Wendling2010-12-031-2/+6
| | | | | | | | | <MCInst 2251 <MCOperand Reg:70> <MCOperand Reg:66> <MCOperand Imm:0> <MCOperand Reg:0> <MCOperand Imm:14> <MCOperand Reg:0>> Notice that the "reg" here is 0, which is an invalid register. Put a check in the code for this to prevent crashing. llvm-svn: 120766
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