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| author | Jim Grosbach <grosbach@apple.com> | 2010-12-14 22:28:03 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2010-12-14 22:28:03 +0000 |
| commit | 509dc2a70070e19aff8801082ab9a92c8624512e (patch) | |
| tree | 7b000b363ebbda251a8a9df70028428c86f37587 /llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp | |
| parent | 6ea3053824c5a9288b23943085f69749523e3b5f (diff) | |
| download | bcm5719-llvm-509dc2a70070e19aff8801082ab9a92c8624512e.tar.gz bcm5719-llvm-509dc2a70070e19aff8801082ab9a92c8624512e.zip | |
Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755
llvm-svn: 121798
Diffstat (limited to 'llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp index 0924591a60c..2770d6e5a50 100644 --- a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -55,6 +55,7 @@ public: { "fixup_arm_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsAligned}, +{ "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsAligned}, @@ -135,6 +136,8 @@ public: /// ADR label target. uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const; + uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl<MCFixup> &Fixups) const; uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const; @@ -559,6 +562,16 @@ getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, Fixups); } +/// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label +/// target. +uint32_t ARMMCCodeEmitter:: +getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl<MCFixup> &Fixups) const { + assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!"); + return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10, + Fixups); +} + /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg' /// operand. uint32_t ARMMCCodeEmitter:: |
