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| author | Owen Anderson <resistor@mac.com> | 2010-12-13 22:51:08 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2010-12-13 22:51:08 +0000 |
| commit | 9a4d42855d2f21239332e69ecb3cfdd1524b9738 (patch) | |
| tree | bc3e1b774512cf44c9bb3a029d15281a3e31820c /llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp | |
| parent | c4bf5cac9fe8b68b755fc07d6890e443ba594dd3 (diff) | |
| download | bcm5719-llvm-9a4d42855d2f21239332e69ecb3cfdd1524b9738.tar.gz bcm5719-llvm-9a4d42855d2f21239332e69ecb3cfdd1524b9738.zip | |
Revert r121721, which broke buildbots.
llvm-svn: 121726
Diffstat (limited to 'llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp index 8dca2c35c65..7f34ee96e37 100644 --- a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -56,8 +56,6 @@ public: { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsAligned}, { "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel }, -{ "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | - MCFixupKindInfo::FKF_IsAligned}, { "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, @@ -135,9 +133,6 @@ public: /// ADR label target. uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const; - uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl<MCFixup> &Fixups) const; - /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' /// operand. @@ -549,16 +544,6 @@ getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, Fixups); } -/// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label -/// target. -uint32_t ARMMCCodeEmitter:: -getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl<MCFixup> &Fixups) const { - assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!"); - return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12, - Fixups); -} - /// getTAddrModeRegRegOpValue - Return encoding info for 'reg + reg' operand. uint32_t ARMMCCodeEmitter:: getTAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, |
