summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
diff options
context:
space:
mode:
authorOwen Anderson <resistor@mac.com>2010-12-07 00:45:21 +0000
committerOwen Anderson <resistor@mac.com>2010-12-07 00:45:21 +0000
commit99ea8a3510012e7c7eac67543c0c3b36ea0a1716 (patch)
tree8e4d753c27e2eeda40f3f6af7ed06e362a14a96f /llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
parenta40433a33ae83fa0d4797123b082dd5658acfa00 (diff)
downloadbcm5719-llvm-99ea8a3510012e7c7eac67543c0c3b36ea0a1716.tar.gz
bcm5719-llvm-99ea8a3510012e7c7eac67543c0c3b36ea0a1716.zip
Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it.
llvm-svn: 121082
Diffstat (limited to 'llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp11
1 files changed, 8 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
index b8939a1531c..b0113476fa8 100644
--- a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
@@ -462,13 +462,18 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
bool isAdd = true;
// If The first operand isn't a register, we have a label reference.
const MCOperand &MO = MI.getOperand(OpIdx);
- if (!MO.isReg()) {
+ const MCOperand &MO2 = MI.getOperand(OpIdx+1);
+ if (!MO.isReg() || (MO.getReg() == ARM::PC && MO2.isExpr())) {
Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
Imm12 = 0;
isAdd = false ; // 'U' bit is set as part of the fixup.
- assert(MO.isExpr() && "Unexpected machine operand type!");
- const MCExpr *Expr = MO.getExpr();
+ const MCExpr *Expr = 0;
+ if (!MO.isReg())
+ Expr = MO.getExpr();
+ else
+ Expr = MO2.getExpr();
+
MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
Fixups.push_back(MCFixup::Create(0, Expr, Kind));
OpenPOWER on IntegriCloud