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author | Bill Wendling <isanbard@gmail.com> | 2010-12-15 08:51:02 +0000 |
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committer | Bill Wendling <isanbard@gmail.com> | 2010-12-15 08:51:02 +0000 |
commit | 03e7576deef3ed9dbde65462a1a0044728614da8 (patch) | |
tree | b1cf3c39927e6828e8ac8ba0dd7279a45c1c9fe1 /llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp | |
parent | 844f6b6cfb8b487ec8dbbe90dd35340e26e00445 (diff) | |
download | bcm5719-llvm-03e7576deef3ed9dbde65462a1a0044728614da8.tar.gz bcm5719-llvm-03e7576deef3ed9dbde65462a1a0044728614da8.zip |
Add fixups for Thumb LDR/STR instructions.
llvm-svn: 121858
Diffstat (limited to 'llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp')
-rw-r--r-- | llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp index c633825adfe..db68f359a2c 100644 --- a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -68,6 +68,7 @@ public: { "fixup_arm_thumb_blx", 7, 21, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_arm_thumb_cp", 1, 8, MCFixupKindInfo::FKF_IsPCRel }, +{ "fixup_arm_thumb_ldst", 1, 8, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_arm_thumb_bcc", 1, 8, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_arm_movt_hi16", 0, 16, 0 }, { "fixup_arm_movw_lo16", 0, 16, 0 }, @@ -213,7 +214,7 @@ public: /// getAddrModeISOpValue - Encode the t_addrmode_is# operands. uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl<MCFixup> &) const; + SmallVectorImpl<MCFixup> &Fixups) const; /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands. uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, @@ -817,14 +818,23 @@ getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, /// getAddrModeISOpValue - Encode the t_addrmode_is# operands. uint32_t ARMMCCodeEmitter:: getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl<MCFixup> &) const { + SmallVectorImpl<MCFixup> &Fixups) const { // [Rn, #imm] // {7-3} = imm5 // {2-0} = Rn const MCOperand &MO = MI.getOperand(OpIdx); const MCOperand &MO1 = MI.getOperand(OpIdx + 1); unsigned Rn = getARMRegisterNumbering(MO.getReg()); - unsigned Imm5 = MO1.getImm(); + unsigned Imm5 = 0; + + if (MO1.isExpr()) { + const MCExpr *Expr = MO.getExpr(); + MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_thumb_ldst); + Fixups.push_back(MCFixup::Create(0, Expr, Kind)); + } else { + Imm5 = MO1.getImm(); + } + return ((Imm5 & 0x1f) << 3) | Rn; } |