| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | ARM: introduce llvm.arm.undefined intrinsic | Saleem Abdulrasool | 2014-05-22 | 1 | -2/+2 |
| * | ARM: implement support for the UDF mnemonic | Saleem Abdulrasool | 2014-05-14 | 1 | -0/+9 |
| * | Add support bswap16 to/from memory compiling to rev16 on ARM/Thumb | Louis Gerbarg | 2014-05-12 | 1 | -0/+12 |
| * | ARM: remove @llvm.arm.sevl | Saleem Abdulrasool | 2014-04-25 | 1 | -1/+0 |
| * | ARM: provide a new generic hint intrinsic | Saleem Abdulrasool | 2014-04-25 | 1 | -1/+2 |
| * | ARM: constrain Thumb LDRLIT pseudo-instructions to r0-r7. | Tim Northover | 2014-01-13 | 1 | -4/+5 |
| * | ARM MachO: sort out isTargetDarwin/isTargetIOS/... checks. | Tim Northover | 2014-01-06 | 1 | -4/+4 |
| * | ARM: bkpt has an implicit immediate constant 0 | Saleem Abdulrasool | 2013-12-23 | 1 | -0/+2 |
| * | ARM: add pseudo-instructions for lit-pool global materialisation | Tim Northover | 2013-12-02 | 1 | -0/+13 |
| * | ARM: remove unused patterns. | Tim Northover | 2013-11-25 | 1 | -2/+1 |
| * | Make ARM hint ranges consistent, and add tests for these ranges | Artyom Skrobov | 2013-10-23 | 1 | -1/+0 |
| * | Add hint disassembly syntax for 16-bit Thumb hint instructions. | Richard Barton | 2013-10-18 | 1 | -22/+19 |
| * | ARM: allow cortex-m0 to use hint instructions | Tim Northover | 2013-10-07 | 1 | -5/+5 |
| * | [ARM] Warn on deprecated IT blocks in v8 AArch32 assembly. | Amara Emerson | 2013-10-03 | 1 | -1/+1 |
| * | [ARM] Introduce the 'sevl' instruction in ARMv8. | Joey Gouly | 2013-10-01 | 1 | -0/+5 |
| * | Add AArch32 DCPS{1,2,3} and HLT instructions. | Richard Barton | 2013-09-05 | 1 | -0/+7 |
| * | ARM: use TableGen patterns to select CMOV operations. | Tim Northover | 2013-08-22 | 1 | -3/+3 |
| * | This fixes three issues related to Thumb literal loads: | Mihai Popa | 2013-08-15 | 1 | -3/+0 |
| * | Fix assembling of Thumb2 branch instructions. | Mihai Popa | 2013-08-09 | 1 | -1/+3 |
| * | This adds range checking for "ldr Rn, [pc, #imm]" Thumb | Mihai Popa | 2013-07-22 | 1 | -23/+20 |
| * | This corrects the implementation of Thumb ADR instruction. There are three i... | Mihai Popa | 2013-07-03 | 1 | -5/+16 |
| * | ARM sched model: Add branch thumb instructions | Arnold Schwaighofer | 2013-06-06 | 1 | -18/+21 |
| * | ARM sched model: Add more ALU and CMP thumb instructions | Arnold Schwaighofer | 2013-06-06 | 1 | -46/+61 |
| * | Revert series of sched model patches until I figure out what is going on. | Arnold Schwaighofer | 2013-06-04 | 1 | -82/+64 |
| * | ARM sched model: Add branch thumb instructions | Arnold Schwaighofer | 2013-06-04 | 1 | -18/+21 |
| * | ARM sched model: Add more ALU and CMP thumb instructions | Arnold Schwaighofer | 2013-06-04 | 1 | -46/+61 |
| * | Mark the Int_eh_sjlj_dispatchsetup pseudo instruction as clobbering all | Chad Rosier | 2012-11-06 | 1 | -4/+0 |
| * | ARM: Better disassembly for pc-relative LDR. | Jim Grosbach | 2012-10-30 | 1 | -0/+1 |
| * | Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. S... | Sylvestre Ledru | 2012-09-27 | 1 | -1/+1 |
| * | Fix a typo 'iff' => 'if' | Sylvestre Ledru | 2012-09-27 | 1 | -1/+1 |
| * | Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ... | Jakob Stoklund Olesen | 2012-08-28 | 1 | -41/+6 |
| * | Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM. | Jakob Stoklund Olesen | 2012-08-27 | 1 | -6/+41 |
| * | Missed tLEApcrelJT. | Jakob Stoklund Olesen | 2012-08-24 | 1 | -0/+1 |
| * | Remove variable_ops from ARM call instructions. | Jakob Stoklund Olesen | 2012-07-13 | 1 | -6/+6 |
| * | (sub X, imm) gets canonicalized to (add X, -imm) | Evan Cheng | 2012-06-23 | 1 | -3/+0 |
| * | Fix typos found by http://github.com/lyda/misspell-check | Benjamin Kramer | 2012-06-02 | 1 | -1/+1 |
| * | Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits | Kevin Enderby | 2012-05-03 | 1 | -7/+8 |
| * | Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures. | Richard Barton | 2012-05-02 | 1 | -4/+8 |
| * | ARM: Thumb add(sp plus register) asm constraints. | Jim Grosbach | 2012-04-27 | 1 | -2/+2 |
| * | ARM: Tweak tADDrSP definition for consistent operand order. | Jim Grosbach | 2012-04-27 | 1 | -2/+2 |
| * | ARM add missing Thumb1 two-operand aliases for shift-by-immediate. | Jim Grosbach | 2012-04-11 | 1 | -0/+8 |
| * | Eliminate iOS-specific tail call instructions. | Jakob Stoklund Olesen | 2012-04-06 | 1 | -8/+4 |
| * | Deduplicate ARM call-related instructions. | Jakob Stoklund Olesen | 2012-04-06 | 1 | -44/+7 |
| * | ARM assembly aliases for add negative immediates using sub. | Jim Grosbach | 2012-04-05 | 1 | -0/+11 |
| * | Switch ARM target to register masks. | Jakob Stoklund Olesen | 2012-02-24 | 1 | -14/+4 |
| * | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu | 2012-02-18 | 1 | -1/+1 |
| * | Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE... | James Molloy | 2012-02-09 | 1 | -0/+1 |
| * | Rename pattern for clarity. | Jim Grosbach | 2012-01-18 | 1 | -4/+3 |
| * | Use RegisterTuples to generate pseudo-registers. | Jakob Stoklund Olesen | 2012-01-13 | 1 | -4/+10 |
| * | Add variants of the dispatchsetup pseudo for Thumb and !VFP. <rdar://10620138> | Bob Wilson | 2011-12-22 | 1 | -0/+4 |
