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authorJim Grosbach <grosbach@apple.com>2012-04-11 00:15:16 +0000
committerJim Grosbach <grosbach@apple.com>2012-04-11 00:15:16 +0000
commitad66de155bbdb01bc2e0ece769bf150203bd1a63 (patch)
treee748ac0cb0ff4fdf35b62099caa46749e056edbc /llvm/lib/Target/ARM/ARMInstrThumb.td
parentaca6c822e6019503232a0da2995d58e1ca7fc5c1 (diff)
downloadbcm5719-llvm-ad66de155bbdb01bc2e0ece769bf150203bd1a63.tar.gz
bcm5719-llvm-ad66de155bbdb01bc2e0ece769bf150203bd1a63.zip
ARM add missing Thumb1 two-operand aliases for shift-by-immediate.
rdar://11222742 llvm-svn: 154457
Diffstat (limited to 'llvm/lib/Target/ARM/ARMInstrThumb.td')
-rw-r--r--llvm/lib/Target/ARM/ARMInstrThumb.td8
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td
index b9ef6925b51..6335229d3c2 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb.td
@@ -1407,3 +1407,11 @@ def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
def : tInstAlias<"neg${s}${p} $Rd, $Rm",
(tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>;
+
+// Implied destination operand forms for shifts.
+def : tInstAlias<"lsl${s}${p} $Rdm, $imm",
+ (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>;
+def : tInstAlias<"lsr${s}${p} $Rdm, $imm",
+ (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;
+def : tInstAlias<"asr${s}${p} $Rdm, $imm",
+ (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;
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