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| author | Tim Northover <tnorthover@apple.com> | 2013-10-07 11:10:47 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2013-10-07 11:10:47 +0000 |
| commit | f86d1f0b7742806d5fe1469044e2a384a73057a0 (patch) | |
| tree | a7f0a661bbe001d5cc49fe4dbf22f251ec0f3195 /llvm/lib/Target/ARM/ARMInstrThumb.td | |
| parent | 17a44966be8655ccc7772d842bda554f72cedcbd (diff) | |
| download | bcm5719-llvm-f86d1f0b7742806d5fe1469044e2a384a73057a0.tar.gz bcm5719-llvm-f86d1f0b7742806d5fe1469044e2a384a73057a0.zip | |
ARM: allow cortex-m0 to use hint instructions
The hint instructions ("nop", "yield", etc) are mostly Thumb2-only, but have
been ported across to the v6M architecture. Fortunately, v6M seems to sit
nicely between v6 (thumb-1 only) and v6T2, so we can add a feature for it
fairly easily.
rdar://problem/15144406
llvm-svn: 192097
Diffstat (limited to 'llvm/lib/Target/ARM/ARMInstrThumb.td')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb.td | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td index 458254ee625..9712ed3274f 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb.td @@ -271,23 +271,23 @@ class T1SystemEncoding<bits<8> opc> def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", []>, T1SystemEncoding<0x00>, // A8.6.110 - Requires<[IsThumb2]>; + Requires<[IsThumb, HasV6M]>; def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", []>, T1SystemEncoding<0x10>, // A8.6.410 - Requires<[IsThumb2]>; + Requires<[IsThumb, HasV6M]>; def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", []>, T1SystemEncoding<0x20>, // A8.6.408 - Requires<[IsThumb2]>; + Requires<[IsThumb, HasV6M]>; def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", []>, T1SystemEncoding<0x30>, // A8.6.409 - Requires<[IsThumb2]>; + Requires<[IsThumb, HasV6M]>; def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", []>, T1SystemEncoding<0x40>, // A8.6.157 - Requires<[IsThumb2]>; + Requires<[IsThumb, HasV6M]>; def tSEVL : T1pI<(outs), (ins), NoItinerary, "sevl", "", [(int_arm_sevl)]>, T1SystemEncoding<0x50>, |
