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| author | Chad Rosier <mcrosier@apple.com> | 2012-11-06 23:05:24 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@apple.com> | 2012-11-06 23:05:24 +0000 |
| commit | 1ec8e404fc94cb5b954dbb8756f0b3640fd3796f (patch) | |
| tree | 69fc53ed3c89ebb05e689a2847ac067e84d31ab3 /llvm/lib/Target/ARM/ARMInstrThumb.td | |
| parent | 8d2c22900659fbd7c0bfb71262161d2a4f10a480 (diff) | |
| download | bcm5719-llvm-1ec8e404fc94cb5b954dbb8756f0b3640fd3796f.tar.gz bcm5719-llvm-1ec8e404fc94cb5b954dbb8756f0b3640fd3796f.zip | |
Mark the Int_eh_sjlj_dispatchsetup pseudo instruction as clobbering all
registers. Previously, the register we being marked as implicitly defined, but
not killed. In some cases this would cause the register scavenger to spill a
dead register.
Also, use an empty register mask to simplify the logic and to reduce the memory
footprint.
rdar://12592448
llvm-svn: 167499
Diffstat (limited to 'llvm/lib/Target/ARM/ARMInstrThumb.td')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb.td | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td index a5c0bc6740e..ae7a5c00bd7 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb.td @@ -1247,10 +1247,6 @@ def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch), [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, Requires<[IsThumb, IsIOS]>; -let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ], - isBarrier = 1 in -def tInt_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>; - //===----------------------------------------------------------------------===// // Non-Instruction Patterns // |
