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| author | Saleem Abdulrasool <compnerd@compnerd.org> | 2014-04-25 17:24:24 +0000 |
|---|---|---|
| committer | Saleem Abdulrasool <compnerd@compnerd.org> | 2014-04-25 17:24:24 +0000 |
| commit | 7e7c2f9ca69b87a1ff1b0030dfddf1e782c2c31d (patch) | |
| tree | a881c39f262a63d743989f679927a5a0f37e6553 /llvm/lib/Target/ARM/ARMInstrThumb.td | |
| parent | 01bbd1b1c379acfd740be2d2a5845db508b2825d (diff) | |
| download | bcm5719-llvm-7e7c2f9ca69b87a1ff1b0030dfddf1e782c2c31d.tar.gz bcm5719-llvm-7e7c2f9ca69b87a1ff1b0030dfddf1e782c2c31d.zip | |
ARM: provide a new generic hint intrinsic
Introduce the llvm.arm.hint(i32) intrinsic that can be used to inject hints into
the instruction stream. This is particularly useful for generating IR from a
compiler where the user may inject an intrinsic (e.g. __yield). These are then
pattern substituted into the correct instruction which already existed.
llvm-svn: 207242
Diffstat (limited to 'llvm/lib/Target/ARM/ARMInstrThumb.td')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb.td | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td index 754295f93fd..ed72d24a811 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb.td @@ -269,7 +269,8 @@ class T1SystemEncoding<bits<8> opc> let Inst{7-0} = opc; } -def tHINT : T1pI<(outs), (ins imm0_15:$imm), NoItinerary, "hint", "\t$imm", []>, +def tHINT : T1pI<(outs), (ins imm0_15:$imm), NoItinerary, "hint", "\t$imm", + [(int_arm_hint imm0_15:$imm)]>, T1SystemEncoding<0x00>, Requires<[IsThumb, HasV6M]> { bits<4> imm; |
