diff options
| author | David Green <david.green@arm.com> | 2019-09-03 11:06:24 +0000 |
|---|---|---|
| committer | David Green <david.green@arm.com> | 2019-09-03 11:06:24 +0000 |
| commit | 61973d978bf95059cacb7d91ef558046d349eacd (patch) | |
| tree | 12c57b5dc9a677f7934f356a0575fef51b49002c /llvm/lib/Target/ARM/ARMISelLowering.cpp | |
| parent | 54904aba474723d6cdfff4d34401863bfcb68d8b (diff) | |
| download | bcm5719-llvm-61973d978bf95059cacb7d91ef558046d349eacd.tar.gz bcm5719-llvm-61973d978bf95059cacb7d91ef558046d349eacd.zip | |
[ARM] Invert CSEL predicates if the opposite is a simpler constant to materialise
This moves ConstantMaterializationCost into ARMBaseInstrInfo so that it can
also be used in ISel Lowering, adding codesize values to the computed costs, to
be able to compare either approximate instruction counts or codesize costs.
It also adds a HasLowerConstantMaterializationCost, which compares the
ConstantMaterializationCost of two values, returning true if the first is
smaller either in instruction count/codesize, or falling back to the other in
the case that they are equal.
This is used in constant CSEL lowering to invert the predicate if the opposite
is easier to materialise.
Differential revision: https://reviews.llvm.org/D66701
llvm-svn: 370741
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 0239d6af8ad..907517461e7 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -4841,6 +4841,15 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { } if (Opcode) { + // If one of the constants is cheaper than another, materialise the + // cheaper one and let the csel generate the other. + if (Opcode != ARMISD::CSINC && + HasLowerConstantMaterializationCost(FVal, TVal, Subtarget)) { + std::swap(TrueVal, FalseVal); + std::swap(TVal, FVal); + CC = ISD::getSetCCInverse(CC, true); + } + // Attempt to use ZR checking TVal is 0, possibly inverting the condition // to get there. CSINC not is invertable like the other two (~(~a) == a, // -(-a) == a, but (a+1)+1 != a). |

