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path: root/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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* AMDGPU: Create emergency stack slots during frame loweringMatt Arsenault2015-11-061-0/+1
* AMDGPU: Remove unused scratch resource operandsMatt Arsenault2015-11-061-72/+129
* AMDGPU: Fix hardcoded alignment of spill.Matt Arsenault2015-11-061-2/+1
* AMDGPU: Also track whether SGPRs were spilledMatt Arsenault2015-11-051-0/+2
* AMDGPU: Fix assert when legalizing atomic operandsMatt Arsenault2015-11-051-15/+51
* AMDGPU: Make findUsedSGPR more readableMatt Arsenault2015-11-031-7/+18
* AMDGPU: Simplify VOP3 operand legalization.Matt Arsenault2015-10-211-41/+49
* AMDGPU: Fix not checking implicit operands in verifyInstructionMatt Arsenault2015-10-211-15/+29
* AMDGPU: Add MachineInstr overloads for instruction format testsMatt Arsenault2015-10-201-30/+26
* AMDGPU: Use explicit register size indirect pseudosMatt Arsenault2015-10-071-1/+1
* AMDGPU/SI: Add verifier check for exec readsMatt Arsenault2015-10-021-0/+10
* AMDGPU/SI: Don't set DATA_FORMAT if ADD_TID_ENABLE is setMarek Olsak2015-09-291-0/+13
* AMDGPU: Factor switch into separate functionMatt Arsenault2015-09-281-21/+27
* AMDGPU: Fix splitting x16 SMRD loadsMatt Arsenault2015-09-281-2/+2
* AMDGPU: Fix moving SMRD loads with literal offsets on CIMatt Arsenault2015-09-281-3/+9
* AMDGPU: Fix splitting SMRD with large offsetMatt Arsenault2015-09-281-1/+1
* Improved the interface of methods commuting operands, improved X86-FMA3 mem-f...Andrew Kaylor2015-09-281-16/+37
* AMDGPU: Construct new buffer instruction when moving SMRDMatt Arsenault2015-09-251-30/+37
* AMDGPU: Re-justify workaround and fix worked around problemMatt Arsenault2015-09-251-18/+42
* AMDGPU: Don't create REG_SEQUENCE with SGPR dest and VGPR sourcesMatt Arsenault2015-09-251-6/+15
* AMDGPU: Return after instruction is processed.Matt Arsenault2015-09-241-0/+4
* AMDGPU: Remove another unnecessary check from commuteInstructionMatt Arsenault2015-09-241-5/+0
* AMDGPU: Reduce number of copies emittedMatt Arsenault2015-09-241-5/+9
* AMDGPU: Remove unnecessary checkMatt Arsenault2015-09-221-4/+0
* AMDGPU/SI: Fix more cases of losing exec operandsMatt Arsenault2015-09-101-3/+1
* AMDGPU: Extract full 64-bit subregister and use subregsMatt Arsenault2015-09-091-35/+29
* AMDGPU: Fix adding redundant implicit operandsMatt Arsenault2015-09-011-11/+7
* AMDGPU: Set mem operands for spill instructionsMatt Arsenault2015-08-291-13/+30
* AMDGPU: Fix dropping mem operands when moving to VALUMatt Arsenault2015-08-291-11/+12
* AMDGPU: Delete dead codeMatt Arsenault2015-08-261-54/+0
* AMDGPU: Don't reprocess instructions when splitting i64 bcntMatt Arsenault2015-08-261-4/+5
* AMDGPU: Fix not moving users of s_bfe_i64 to VALUMatt Arsenault2015-08-261-0/+2
* AMDGPU: Don't create intermediate SALU instructionsMatt Arsenault2015-08-261-27/+40
* Fix some comment typos.Benjamin Kramer2015-08-081-1/+1
* AMDGPU/SI: Remove VCCRegMatt Arsenault2015-08-081-1/+1
* AMDGPU/SI: Remove EXECRegMatt Arsenault2015-08-051-5/+0
* AMDGPU/SI: Add implicit register operands in the correct order.Alex Lorenz2015-07-311-19/+1
* AMDGPU/SI: Simplify moveSMRDToVALU()Tom Stellard2015-07-301-11/+9
* AMDGPU/SI: Remove isTriviallyReMaterializable() function from SIInstrInfoTom Stellard2015-07-301-12/+0
* AMDGPU/SI: Fix read2 merging into a super register.Matt Arsenault2015-07-141-2/+1
* AMDGPU/SI: Select mad patterns to v_mac_f32Tom Stellard2015-07-131-5/+51
* AMDGPU/SI: Fix crash on physical registers in SIInstrInfo::isOperandLegal()Tom Stellard2015-07-091-1/+4
* AMDPGU/SI: Use correct resource descriptors for VI on HSATom Stellard2015-06-261-1/+6
* AMDGPU: really don't commute REV opcodes if the target variant doesn't existMarek Olsak2015-06-261-8/+12
* Fix "the the" in comments.Eric Christopher2015-06-191-1/+1
* [TargetInstrInfo] Rename getLdStBaseRegImmOfs and implement for x86.Sanjoy Das2015-06-151-5/+5
* R600 -> AMDGPU renameTom Stellard2015-06-131-0/+2723
* Revert "AMDGPU: Add core backend files for R600/SI codegen v6"Tom Stellard2012-07-161-103/+0
* AMDGPU: Add core backend files for R600/SI codegen v6Tom Stellard2012-07-161-0/+103
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