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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-11-03 22:30:15 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-11-03 22:30:15 +0000 |
commit | 6c0674112aa375f4ff61ee54e48a3ce244e10525 (patch) | |
tree | a7bda9234299024922d59424c9e4f25e26fe8802 /llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | |
parent | 782c03bb7e80dc96043ee1d44bea8fcbb467cf76 (diff) | |
download | bcm5719-llvm-6c0674112aa375f4ff61ee54e48a3ce244e10525.tar.gz bcm5719-llvm-6c0674112aa375f4ff61ee54e48a3ce244e10525.zip |
AMDGPU: Make findUsedSGPR more readable
Add more comments etc.
llvm-svn: 251996
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIInstrInfo.cpp')
-rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 25 |
1 files changed, 18 insertions, 7 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index e37a619cc5a..26f61039dfa 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -2665,6 +2665,7 @@ const TargetRegisterClass *SIInstrInfo::getDestEquivalentVGPRClass( } } +// Find the one SGPR operand we are allowed to use. unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI, int OpIndices[3]) const { const MCInstrDesc &Desc = MI->getDesc(); @@ -2691,15 +2692,22 @@ unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI, break; const MachineOperand &MO = MI->getOperand(Idx); - if (RI.isSGPRClassID(Desc.OpInfo[Idx].RegClass)) - SGPRReg = MO.getReg(); + if (!MO.isReg()) + continue; - if (MO.isReg() && RI.isSGPRClass(MRI.getRegClass(MO.getReg()))) - UsedSGPRs[i] = MO.getReg(); - } + // Is this operand statically required to be an SGPR based on the operand + // constraints? + const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass); + bool IsRequiredSGPR = RI.isSGPRClass(OpRC); + if (IsRequiredSGPR) + return MO.getReg(); - if (SGPRReg != AMDGPU::NoRegister) - return SGPRReg; + // If this could be a VGPR or an SGPR, Check the dynamic register class. + unsigned Reg = MO.getReg(); + const TargetRegisterClass *RegRC = MRI.getRegClass(Reg); + if (RI.isSGPRClass(RegRC)) + UsedSGPRs[i] = Reg; + } // We don't have a required SGPR operand, so we have a bit more freedom in // selecting operands to move. @@ -2711,6 +2719,9 @@ unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI, // V_FMA_F32 v0, s0, s0, s0 -> No moves // V_FMA_F32 v0, s0, s1, s0 -> Move s1 + // TODO: If some of the operands are 64-bit SGPRs and some 32, we should + // prefer those. + if (UsedSGPRs[0] != AMDGPU::NoRegister) { if (UsedSGPRs[0] == UsedSGPRs[1] || UsedSGPRs[0] == UsedSGPRs[2]) SGPRReg = UsedSGPRs[0]; |