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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-11-05 05:27:10 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-11-05 05:27:10 +0000 |
| commit | 5b22dfa65d5c98102f12bf2e6ad7392315930fad (patch) | |
| tree | fee62a626ceb9df38aec61ca39c5c6a9f0e22319 /llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | |
| parent | d41c0dbff0caf01f9592647960a05a44339413a3 (diff) | |
| download | bcm5719-llvm-5b22dfa65d5c98102f12bf2e6ad7392315930fad.tar.gz bcm5719-llvm-5b22dfa65d5c98102f12bf2e6ad7392315930fad.zip | |
AMDGPU: Also track whether SGPRs were spilled
llvm-svn: 252145
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index b6e1a9cbf6a..9068c177878 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -484,6 +484,8 @@ void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, int Opcode = -1; if (RI.isSGPRClass(RC)) { + MFI->setHasSpilledSGPRs(); + // We are only allowed to create one new instruction when spilling // registers, so we need to use pseudo instruction for spilling // SGPRs. |
