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path: root/llvm/lib/Target/AMDGPU
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* Reduce the size of MCRelaxableFragment.Akira Hatanaka2015-11-141-2/+4
* [MCTargetAsmParser] Move the member varialbes that referenceAkira Hatanaka2015-11-141-9/+7
* AMDGPU: Add stony supportTom Stellard2015-11-131-0/+4
* Revert "Remove unnecessary call to getAllocatableRegClass"Tom Stellard2015-11-123-6/+16
* AMDGPU: Print more fields in commentsMatt Arsenault2015-11-111-3/+14
* AMDGPU: Remove dead codeMatt Arsenault2015-11-111-33/+2
* AMDGPU: Set isAllocatable = 0 on VS_32/VS_64Matt Arsenault2015-11-113-16/+6
* AMDGPU/SI: Refactor VOP[12C] tablegen definitionsTom Stellard2015-11-062-97/+75
* AMDGPU: Cleanup includesMatt Arsenault2015-11-062-6/+4
* AMDGPU: Create emergency stack slots during frame loweringMatt Arsenault2015-11-067-14/+89
* AMDGPU: Remove unused scratch resource operandsMatt Arsenault2015-11-062-75/+131
* AMDGPU: Add pass to detect used kernel featuresMatt Arsenault2015-11-064-0/+138
* AMDGPU: Fix hardcoded alignment of spill.Matt Arsenault2015-11-062-13/+12
* AMDGPU: Hack for VS_32 register pressureMatt Arsenault2015-11-062-4/+17
* AMDGPU/SI: Emit HSA kernels with symbol type STT_AMDGPU_HSA_KERNELTom Stellard2015-11-066-0/+60
* AMDGPU: Also track whether SGPRs were spilledMatt Arsenault2015-11-053-2/+20
* AMDGPU: Print number user SGPRsMatt Arsenault2015-11-051-0/+6
* AMDGPU: Disallow s[102:103] on VI in assemblerMatt Arsenault2015-11-051-2/+28
* AMDGPU: Fix assert when legalizing atomic operandsMatt Arsenault2015-11-053-15/+59
* AMDGPU: Make addr64 atomic operand order consistentMatt Arsenault2015-11-051-2/+2
* AMDGPU: Fix typoMatt Arsenault2015-11-051-2/+2
* AMDGPU: Make flat_scratch name consistentMatt Arsenault2015-11-031-3/+3
* AMDGPU: Fix asserts on invalid register rangesMatt Arsenault2015-11-031-5/+13
* AMDGPU: Fix off by one error in register parsingMatt Arsenault2015-11-031-4/+5
* AMDGPU: s[102:103] is unavailable on VIMatt Arsenault2015-11-031-1/+10
* AMDGPU: Define correct number of SGPRsMatt Arsenault2015-11-032-6/+10
* AMDGPU: Make findUsedSGPR more readableMatt Arsenault2015-11-031-7/+18
* AMDGPU: Initialize SIFixSGPRCopies so -print-after worksMatt Arsenault2015-11-033-8/+15
* AMDGPU: Alphabetize includesMatt Arsenault2015-11-031-1/+1
* ScheduleDAGInstrs: Remove IsPostRA flag; NFCMatthias Braun2015-11-031-2/+1
* AMDGPU: Stop assuming vreg for build_vectorMatt Arsenault2015-11-022-20/+40
* AMDGPU: Error on graphics shaders with HSAMatt Arsenault2015-11-021-0/+8
* AMDGPU: Distribute SGPR->VGPR copies of REG_SEQUENCEMatt Arsenault2015-11-021-23/+89
* AMDGPU/SI: handle undef for llvm.SI.packf16Marek Olsak2015-10-291-0/+4
* AMDGPU/SI: use S_OR for fneg (fabs f32)Marek Olsak2015-10-291-2/+1
* AMDGPU/SI: use S_AND for i1 truncMarek Olsak2015-10-291-2/+2
* AMDGPU: Print modifiers when dumping AMDGPUOperandMatt Arsenault2015-10-241-1/+1
* AMDGPU: Fix parsing of 32-bit literals with sign bit setMatt Arsenault2015-10-232-5/+8
* AMDGPU: Fix adding redundant m0 usesMatt Arsenault2015-10-211-2/+0
* AMDGPU: Fix verifier error in SIFoldOperandsMatt Arsenault2015-10-211-1/+4
* AMDGPU: Split DiagnosticInfoUnsupported into its own fileMatt Arsenault2015-10-214-41/+76
* AMDGPU: Simplify VOP3 operand legalization.Matt Arsenault2015-10-213-42/+58
* AMDGPU: Fix not checking implicit operands in verifyInstructionMatt Arsenault2015-10-211-15/+29
* AMDGPU: Add MachineInstr overloads for instruction format testsMatt Arsenault2015-10-207-40/+111
* AMDGPU: Stop reserving v[254:255]Matt Arsenault2015-10-201-4/+0
* Make a bunch of static arrays const.Craig Topper2015-10-182-2/+2
* Don't pretend AMDGPU backend knows how to custom-lower UDIVREM for vector typ...Artyom Skrobov2015-10-151-1/+1
* AMDGPU: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-139-18/+17
* AMDGPU: Refactor isVGPRToSGPRCopyMatt Arsenault2015-10-131-19/+48
* DAGCombiner: Combine extract_vector_elt from build_vectorMatt Arsenault2015-10-122-0/+13
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