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path: root/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
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* Re-commit AMDGPU/GlobalISel: Add support for simple shadersTom Stellard2017-01-301-0/+15
* Revert "AMDGPU/GlobalISel: Add support for simple shaders"Tom Stellard2017-01-301-15/+0
* AMDGPU/GlobalISel: Add support for simple shadersTom Stellard2017-01-301-0/+15
* AMDGPU: Enable FeatureFlatForGlobal on Volcanic IslandsMatt Arsenault2017-01-271-1/+0
* AMDGPU: Implement early ifcvt target hooks.Matt Arsenault2017-01-251-0/+5
* AMDGPU add support for spilling to a user sgpr pointed buffersTom Stellard2017-01-251-7/+16
* Enable FeatureFlatForGlobal on Volcanic IslandsMatt Arsenault2017-01-241-0/+1
* AMDGPU: Combine fp16/fp64 subtarget featuresMatt Arsenault2017-01-231-4/+3
* [AMDGPU] Add subtarget features for SDWA/DPPSam Kolton2017-01-201-0/+10
* [AMDGPU, PowerPC, TableGen] Fix some Clang-tidy modernize and Include What Yo...Eugene Zelenko2016-12-091-5/+12
* [AMDGPU] Scalarization of global uniform loads.Alexander Timofeev2016-12-081-0/+4
* [AMDGPU] Add f16 support (VI+)Konstantin Zhuravlyov2016-11-131-0/+4
* [AMDGPU] Check if type transforms to i16 (VI+) when getting AMDGPUISD::FFBH_U32Konstantin Zhuravlyov2016-11-011-4/+4
* AMDGPU: Use 1/2pi inline imm on VIMatt Arsenault2016-10-291-0/+5
* AMDGPU: Add definitions for scalar store instructionsMatt Arsenault2016-10-281-0/+5
* AMDGPU: Diagnose using too many SGPRsMatt Arsenault2016-10-281-0/+2
* AMDGPU/SI: Handle hazard with > 8 byte VMEM storesTom Stellard2016-10-271-0/+4
* AMDGPU: Refactor processor definition to use ISA version featuresYaxun Liu2016-10-261-1/+4
* AMDGPU : Add a function to enable and disable IEEEBit for SC and shaderWei Ding2016-10-191-0/+4
* AMDGPU/SI: Don't allow unaligned scratch accessTom Stellard2016-10-141-0/+5
* AMDGPU: Add instruction definitions for VGPR indexingMatt Arsenault2016-10-121-0/+10
* AMDGPU/SI: Update ISA version numbers for Tonga and Polaris10/11.Changpeng Fang2016-10-111-0/+1
* [AMDGPU] Ask subtarget if waitcnt instruction is needed before barrier instru...Konstantin Zhuravlyov2016-09-301-0/+6
* AMDGPU/SI: Include implicit arguments in kernarg_segment_byte_sizeTom Stellard2016-09-231-0/+14
* AMDGPU: Use i64 scalar compare instructionsMatt Arsenault2016-09-171-0/+4
* AMDGPU/SI: Add support for triples with the mesa3d operating systemTom Stellard2016-09-161-1/+9
* AMDGPU/SI: Make sure llvm.amdgcn.implicitarg.ptr() is 8-byte aligned for HSATom Stellard2016-09-091-0/+4
* [AMDGPU] Wave and register controlsKonstantin Zhuravlyov2016-09-061-8/+83
* AMDGPU/SI: Implement a custom MachineSchedStrategyTom Stellard2016-08-291-0/+6
* AMDGPU: Fix crashes on memory functionsMatt Arsenault2016-08-111-0/+7
* AMDGPU/SI: Increase SGPR limit to 96 on Tonga/IcelandMarek Olsak2016-08-051-1/+3
* AMDGPU: Delete dead codeMatt Arsenault2016-07-251-6/+0
* AMDGPU: Delete more dead codeMatt Arsenault2016-07-221-33/+4
* AMDGPU: Add feature for unaligned accessMatt Arsenault2016-07-011-0/+5
* Target: Remove unused arguments from overrideSchedPolicy, NFCDuncan P. N. Exon Smith2016-07-011-1/+0
* AMDGPU: Move subtarget feature checks into passesMatt Arsenault2016-06-271-5/+0
* [AMDGPU] Emit debugger prologue and emit the rest of the debugger fields in t...Konstantin Zhuravlyov2016-06-251-0/+10
* AMDGPU: Remove disable-irstructurizer subtarget featureMatt Arsenault2016-06-241-5/+0
* AMDGPU: Cleanup subtarget handling.Matt Arsenault2016-06-241-144/+232
* AMDGPU: Fix i64 global cmpxchgMatt Arsenault2016-06-091-0/+4
* [AMDGPU][NFC] Rename ReserveTrapVGPRs -> ReserveRegsKonstantin Zhuravlyov2016-05-241-3/+3
* AMDGPU: Fix promote alloca pass creating huge arraysMatt Arsenault2016-05-161-1/+10
* [AMDGPU] Move reserved vgpr count for trap handler usage to SIMachineFunction...Konstantin Zhuravlyov2016-04-261-4/+0
* [AMDGPU] Reserve VGPRs for trap handler usage if instructedKonstantin Zhuravlyov2016-04-261-0/+9
* [AMDGPU] Add insert nops pass based on subtarget features instead of cl::optKonstantin Zhuravlyov2016-04-181-0/+5
* [NFC] Header cleanupMehdi Amini2016-04-181-2/+2
* AMDGPU: Add skeleton GlobalIsel implementationTom Stellard2016-04-141-0/+8
* AMDGPU: Add a shader calling conventionNicolai Haehnle2016-04-061-1/+1
* AMDGPU: More bits of frame index are known to be zeroMatt Arsenault2016-02-271-5/+0
* AMDGPU: Split vi-insts subtarget featureMatt Arsenault2016-02-271-1/+10
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